Neue Schulungen
Designing with IP Integrator Tool 101 - WEBINAR
Versal Power and Board Design - Essentials - LIVE ONLINE
Compact Vitis AI
Compact Vitis for Software Designer
Compact Vitis for Acceleration
Professional Vitis
New Features in VHDL 2019 - WEBINAR
Dynamic Function eXchange (DFX) – reloading partial h/w function using Zynq MPSoC - WEBINAR
Versal ACAP System Architecture
Professional Versal ACAP
Expert Versal AI Engine
Compact Versal ACAP for SW Designers
Advanced Versal AI Engine
Compact Versal ACAP for HW Designers
On the development of FPGAs according to DO254 - WEBINAR
Vitis AI – Creating an Edge Inference Solution from a pretrained Model - WEBINAR
Vitis HLS – Getting Started - LIVE ONLINE
Vitis Acceleration Methodology - LIVE ONLINE
Versal AI Engine Essentials - LIVE ONLINE
Versal Architecture Essentials - LIVE ONLINE
Vitis AI – Getting Started - LIVE ONLINE
Real time, low power vision and AI systems - WEBINAR
Introduction into ROS Video Application Acceleration using Kria SOM and Vitis Tools - WEBINAR
Partially Constrained Record Types in VHDL-2008 or: How to wire components effectively? - WEBINAR
Xilinx Versal ACAP – Application acceleration on heterogenous platforms - WEBINAR
Spartan-6 to 7-Series/UltraScale+ Migration - LIVE ONLINE
Kiss the Xilinx 7-Series Hello: How to convert your Spartan-6 Project - WEBINAR
Technik trifft Recht
Gesunde Führung und Mindful Leadership
Kommunikation und Feedback
Vitis HLS
Easy Start with the Kria KV260 Vision AI Starter Kit
Easy Start
FPGA
Advanced Verification with OSVVM - LIVE ONLINE
Advanced Vivado-Tcl-Scripting
Compact FPGA 7 Series
Compact FPGA Schaltungstechnik
Compact UltraScale/UltraScale+
Compact Verilog
Compact VHDL for Simulation
Compact VHDL for Synthesis
Compact VHDL Testbenches and Verification with OSVVM
Continuous Integration
Continuous Integration for EDA Tools - LIVE ONLINE
Debugging Techniques Using the VIVADO Logic Analyzer
Design, Constraining and Verification of Low Speed and High Speed ADC Interfaces - SHORTIE
Designing with the Spartan-7 Family
Designing with the XILINX Analog Mixed Signal Solution
Developing for Mission Critical FPGA & SoC
Dynamic Function eXchange DFX
FPGA Design Techniques - LIVE ONLINE
FPGA Design Techniques Essentials - LIVE ONLINE
FPGA Designer - Langzeitausbildung
FPGA Power Optimization
FPGA-Based Deep Learning (DEEP Neural Networks) Inference Accelerator - WEBINAR
Git
Git for EDA Tool Flows - LIVE ONLINE
Introduction to Verification with OSVVM - LIVE ONLINE
New Features in VHDL 2019 - WEBINAR
On the development of FPGAs according to DO254 - WEBINAR
OSVVM – New Verification IPs - SHORTIE
Partially Constrained Record Types in VHDL-2008 or: How to wire components effectively? - WEBINAR
Professional FPGA
Professional FPGA Schaltungstechnik
Professional VHDL
Professional VHDL Testbenches and Verification with OSVVM
Professional VIVADO
Spartan-6 to 7-Series/UltraScale+ Migration - LIVE ONLINE
SysML-Einführung für Systemingenieure
SystemVerilog – Advanced Verification for FPGA Design
Tcl Schnellstart
UltraScale/UltraScale+ Architecture - LIVE ONLINE
UVM Made Easy for FPGA Designers
VHDL for Simulation - LIVE ONLINE
VHDL for Synthesis - LIVE ONLINE
Vivado Design Flow - LIVE ONLINE
VIVADO Design Suite Static Timing Analysis and XILINX Design Constraints
VIVADO Design Suite Tool Flow
Vivado IP Flow - LIVE ONLINE
Vivado Logic Analyzer - LIVE ONLINE
Vivado Timing Constraints and Analysis - LIVE ONLINE
Embedded
Advanced Versal AI Engine
Advanced ZYNQ Ultrascale+ MPSoC for HW Designers
AXI Interface Technology
Compact Embedded Linux
Compact Python for Embedded
Compact Versal ACAP for HW Designers
Compact Versal ACAP for SW Designers
Compact Vitis AI
Compact Vitis for Acceleration
Compact Vitis for Software Designer
Compact ZYNQ UltraScale+ MPSoC for HW Designers
Compact ZYNQ UltraScale+ MPSoC for SW Designers
Compact ZYNQ-7000 SoC for HW Designers
Compact ZYNQ-7000 SoC for SW Designers
Debugging Multi-Core Designs using Vitis + Cross-Triggered based Debugging using Zynq US+/MPSoC - SHORTIE
Designing with IP Integrator Tool 101 - WEBINAR
Designing with RF Data Converters
Designing with the Zynq UltraScale+ RFSoC - LIVE ONLINE
Developing Multimedia Solutions with the VCU and GStreamer
Dynamic Function eXchange (DFX) – reloading partial h/w function using Zynq MPSoC - WEBINAR
Embedded Design with PetaLinux Tools
Embedded Linux Development with Yocto Project
Embedded Linux Treiberentwicklung
Essentials of Microprocessors
Expert Versal AI Engine
Expert ZYNQ-7000 SoC
FPGA Designer Embedded - Langzeitausbildung
FPGA-Based Deep Learning (DEEP Neural Networks) Inference Accelerator - WEBINAR
High-Speed Ethernet – Hands-On System Development
Introduction into ROS Video Application Acceleration using Kria SOM and Vitis Tools - WEBINAR
Kiss the Xilinx 7-Series Hello: How to convert your Spartan-6 Project - WEBINAR
MicroBlaze Essentials and Workflow - LIVE ONLINE
Migrate to Real-Time OS: Hands-On System Development
Migrating a Vivado SDK - Project to Vitis Unified Software Platform - SHORTIE
Migrating to the Vitis Embedded Software Development - LIVE ONLINE
PCI Express Hands-on System Development
Professional MicroBlaze System Design
Professional Python for Embedded
Professional RFSoC
Professional Versal ACAP
Professional Vitis
Professional ZYNQ UltraScale+ MPSoC
Professional ZYNQ-7000 SoC
Real time, low power vision and AI systems - WEBINAR
Real-Time Control System Development using RTOS
RISC-V Architecture and FPGA Implementation
RISC-V Core Verification and Compliance Testing
Running Multiple OS using XEN Hypervisor for Zynq US+ MPSoC - WEBINAR
Versal ACAP System Architecture
Versal AI Engine Essentials - LIVE ONLINE
Versal Architecture Essentials - LIVE ONLINE
Versal Power and Board Design - Essentials - LIVE ONLINE
Vitis Acceleration Methodology - LIVE ONLINE
Vitis AI – Creating an Edge Inference Solution from a pretrained Model - WEBINAR
Vitis AI – Getting Started - LIVE ONLINE
Vitis HLS
Vitis HLS – Getting Started - LIVE ONLINE
Vitis Tools for Acceleration – Creating a RTL Kernel - WEBINAR
Xilinx Versal ACAP - Creating a Custom Embedded Platform - WEBINAR
Xilinx Versal ACAP - From FPGA to Platform - WEBINAR
Xilinx Versal ACAP – Application acceleration on heterogenous platforms - WEBINAR
Zynq 7000 SoC for the Hardware Designer - LIVE ONLINE
Zynq 7000 SoC for the Software Designer - LIVE ONLINE
Zynq UltraScale+ MPSoC for the Hardware Designer - LIVE ONLINE
Zynq UltraScale+ MPSoC for the Software Designer - LIVE ONLINE
Zynq UltraScale+ MPSoC for the System Architect - LIVE ONLINE
ZYNQ UltraScale+ MPSoC System Architecture
ZYNQ-7000 SoC System Architecture
DSP & Image Processing
Connectivity
DDR4 Interfacing with XILINX FPGAs
Designing an Integrated PCI Express System PCIe Gen3 - LIVE ONLINE
Designing with Ethernet MAC Controllers
Designing with Multi-Gigabit Serial I/O
Designing with PCI Express
Designing with Xilinx Serial Transceivers - LIVE ONLINE
FPGA Board-Design
High-Speed Memory Interfacing
PCIe Protocol Overview - LIVE ONLINE
Professional PCI Express
Signal Integrity
UltraScale FPGAs – Connectivity
VERSAL ACAP Connectivity (5 Tage)
ZYNQ – Board Design and High Speed Interfacing
Online Training
Advanced Verification with OSVVM - LIVE ONLINE
Continuous Integration for EDA Tools - LIVE ONLINE
Debugging Multi-Core Designs using Vitis + Cross-Triggered based Debugging using Zynq US+/MPSoC - SHORTIE
Design, Constraining and Verification of Low Speed and High Speed ADC Interfaces - SHORTIE
Designing an Integrated PCI Express System PCIe Gen3 - LIVE ONLINE
Designing with IP Integrator Tool 101 - WEBINAR
Designing with the Zynq UltraScale+ RFSoC - LIVE ONLINE
Designing with Xilinx Serial Transceivers - LIVE ONLINE
Dynamic Function eXchange (DFX) – reloading partial h/w function using Zynq MPSoC - WEBINAR
Easy Start FPGA Vivado - LIVE ONLINE
FPGA Design Techniques - LIVE ONLINE
FPGA Design Techniques Essentials - LIVE ONLINE
FPGA-Based Deep Learning (DEEP Neural Networks) Inference Accelerator - WEBINAR
Git for EDA Tool Flows - LIVE ONLINE
Introduction into ROS Video Application Acceleration using Kria SOM and Vitis Tools - WEBINAR
Introduction to Verification with OSVVM - LIVE ONLINE
Kiss the Xilinx 7-Series Hello: How to convert your Spartan-6 Project - WEBINAR
MicroBlaze Essentials and Workflow - LIVE ONLINE
Migrating a Vivado SDK - Project to Vitis Unified Software Platform - SHORTIE
Migrating to the Vitis Embedded Software Development - LIVE ONLINE
New Features in VHDL 2019 - WEBINAR
On the development of FPGAs according to DO254 - WEBINAR
OSVVM – New Verification IPs - SHORTIE
Partially Constrained Record Types in VHDL-2008 or: How to wire components effectively? - WEBINAR
PCIe Protocol Overview - LIVE ONLINE
Real time, low power vision and AI systems - WEBINAR
Running Multiple OS using XEN Hypervisor for Zynq US+ MPSoC - WEBINAR
Spartan-6 to 7-Series/UltraScale+ Migration - LIVE ONLINE
UltraScale/UltraScale+ Architecture - LIVE ONLINE
Versal AI Engine Essentials - LIVE ONLINE
Versal Architecture Essentials - LIVE ONLINE
Versal Power and Board Design - Essentials - LIVE ONLINE
VHDL for Simulation - LIVE ONLINE
VHDL for Synthesis - LIVE ONLINE
Vitis Acceleration Methodology - LIVE ONLINE
Vitis AI – Creating an Edge Inference Solution from a pretrained Model - WEBINAR
Vitis AI – Getting Started - LIVE ONLINE
Vitis HLS – Getting Started - LIVE ONLINE
Vitis Tools for Acceleration – Creating a RTL Kernel - WEBINAR
Vivado Design Flow - LIVE ONLINE
Vivado IP Flow - LIVE ONLINE
Vivado Logic Analyzer - LIVE ONLINE
Vivado Timing Constraints and Analysis - LIVE ONLINE
Xilinx Versal ACAP - Creating a Custom Embedded Platform - WEBINAR
Xilinx Versal ACAP - From FPGA to Platform - WEBINAR
Xilinx Versal ACAP – Application acceleration on heterogenous platforms - WEBINAR
Zynq 7000 SoC for the Hardware Designer - LIVE ONLINE
Zynq 7000 SoC for the Software Designer - LIVE ONLINE
Zynq UltraScale+ MPSoC for the Hardware Designer - LIVE ONLINE
Zynq UltraScale+ MPSoC for the Software Designer - LIVE ONLINE
Zynq UltraScale+ MPSoC for the System Architect - LIVE ONLINE