Webinar "First-time Right Methods in ASIC and FPGA Design" -jetzt anmelden-

Vivado High-Level-Synthese for Hardware Designers - LIVE ONLINE

The productivity of FPGA development can be significantly improved with the integral Vivado HLS and should be known to VHDL as well as Verilog developers, since the development effort for many modules can be reduced. The web seminar is aimed at hardware developers who have not yet worked with the Vivado-HLS to show you how to use the tool and what type of modules are suitable for C / C ++ synthesis and thus as an alternative to HDL coding.

The theoretical content is supplemented by exercises carried out by the participant.
 

Duration: 3 mornings of 4 hours each

Times:    9.00 a.m. - 11.00 a.m.    Lecture part 1

              11.00 a.m. - 11.15 a.m.  15 minute break

              11.15 a.m. - 1.15 p.m.    Lecture part 2

Exercises: self paced by the participants. Estimated time for completion appr. 2-3 hours. At the end of a lecture, the exercises to be performed by participants are discussed. The results / sample solutions are presented by the trainer the next day.

After registration: the participant receives the presentation documents in electronic form (PDF) as well as the workbook for the exercises, the login data and a list of 
requirements to be done in advanced.

Course Objectives:

  • Understanding the concept and methodology of Vivado HLS
  • Describe the Vivado HLS Design flow
  • Identify the steps to extract RTL from C
  • Describe the architecture optimization and analyze methods
  • Describe the integration of HLS modules in the Vivado project

Agenda:

  • Basics of the Vivado HLS Tool
  • Performance and Utilization Exploration
  • Directive usage for optimization
  • The HLS UltraFast design methodology
  • Interfacing HLS modules with HDL modules
  • C/C++-Coding and provided DSP Libraries

Labs

Lab1: Introduction to the Vivado HLS Tool Flow

Lab2: Block-Level IO Protocols

Lab3: Port-Level IO Protocols

Lab4: Pipeline for Performance PIPELINE

Lab5: Pipeline for Performance DATAFLOW

Lab6: Optimizing Structures for Performance

Lab7: Improving Area and Resource Utilization

Lab8: Hlx Flow – System Integration


Anwendbare Technologien

  • Xilinx FPGAs, Zynq SoCs, Zynq UltraScale+ MPSoC and RFSoC, Versal

Voraussetzungen

  • Grundkenntnisse der digitalen Signalverarbeitung
  • Grundlegende Kenntnisse der Programmiersprache C/C++
  • Grundkenntnisse der XILINX FPGA-Entwicklung

Termine


23.11.2020 | Online
Training buchen

Dauer und Kosten


Dauer: 3 Tage (je 4 Stunden)

Kosten: 1.500,00 €
netto pro Teilnehmer inklusive ausführlicher Schulungsunterlagen

Ansprechpartner


Michael Schwarz