Vivado Design Flow - LIVE ONLINE

Vivado Design Flow describes the FPGA design process with the Vivado Design Suite. After a general introduction to the FPGA Design Flow, a detailed introduction to the use of the Vivado Project based Design Flow and the Vivado Non-Project based Design Flow follows.

The theoretical content is supplemented by exercises carried out by the participant.

Duration:  3 mornings of 4 hours each

Times:   9.00 a.m. - 11.00 a.m.    Lecture part 1

             11.00 a.m. - 11.15 a.m.   15 minute break

             11.15 a.m. - 1.15 p.m.     Lecture part 2

Exercises:  self paced by the participants. Estimated time for completion appr. 2-3 hours. At the end of a lecture, the exercises to be performed by participants are discussed. The results / sample solutions are presented by the trainer the next day.

After registration: The participant receives the presentation documents in electronic form (PDF) as well as the workbook for the exercises, the login data and a list of 
requirements to be done in advanced.

Course Objectives

• Describe various design flows in the Vivado Design Suite
• Explain how the Vivado tool flow is different from ISE tool flow
• Identify and describe the supported use models in the Vivado Design Suite
• Describe the project mode use model in the Vivado Design Suite
• Describe the design flow using non-project batch mode

Agenda 

• The design flows in the Vivado Design Suite
• How is the Vivado tool flow different from ISE tool flow?
• Supported use models in the Vivado Design Suite
• Project mode use model in the Vivado Design Suit
• Non-project mode use model in the Vivado Design Suite

Anwendbare Technologien

• alle FPGA Technologien

Voraussetzungen

• Grundkenntnisse VHDL oder Verilog