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VHDL for Synthesis - LIVE ONLINE

Programmable logic devices like FPGAs have been established in the daily life. They can be found in mobile phones, IoT devices, cars or cloud data centers. Their area of operation is as broad as their size. FPGAs are used as, but not limited to: protocol adapters, signal converters, or accelerators for video, radar and sensor data processing.

The design of digital circuits in this scale needs a powerful hardware description language which offers different levels of abstraction, so an engineer can create a digital hardware design in a quick and effective way. VHDL fulfills these requirements.

VHDL is a strongly typed hardware description language which prohibits typical programming mistakes in the coding phase. Usually, VHDL is used on the register transfer level (RTL) to design digital circuits of any complexity. Apart from the language constructs for synthesis, VHDL offers a wide range of functionality to describe complex verification models. Thus, it is possible verify digital designs from simple gate up to complicated System-on-Chip (SoC) before going to lab tests.

This live online training will teach the synthesis relevant aspects of the VHDL hardware description language based on the IEEE Std. 1076-2008 language revision. The theoretical knowledge will be deepened with selected examples and labs on PC.

A basic knowledge in digital circuit design (gates, multiplexers, flip-flops, memories), as well as the understanding of basic principles of scripting or programming languages are welcome.


The theoretical content is supplemented by exercises carried out by the participant.

Duration: 4 mornings of 4 hours each

Times:    9.00 a.m. - 11.00 a.m.    Lecture part 1

              11.00 a.m. - 11.15 a.m.  15 minute break

              11.15 a.m. - 1.15 p.m.    Lecture part 2

Exercises: self paced by the participants. Estimated time for completion appr. 2-3 hours. At the end of a lecture, the exercises to be performed by participants are discussed. The results / sample solutions are presented by the trainer the next day.

After registration: the participant receives the presentation documents in electronic form (PDF) as well as the workbook for the exercises, the login data and a list of 
requirements to be done in advanced.

Course Objectives:

  • Vision: Learn an all parallel computer language to describe digital circuits
  • Learn VHDL-2008 language constructs mainly for synthesis
  • Understand parallel execution model
  • Understand how VHDL translates to gates and circuits
  • Create a digital circuit description for an FPGA
  • Run the synthesis and implementation tool flow in Xilinx Vivado
  • Divide a design into hierarchical units
  • Experience coding style, reuse and maintainability with VHDL


  • Introduction into VHDL
    • Language concept
    • Hardware modelling techniques
    • Design flow
  • Hardware Description with VHDL
    • Entity / Architecture
    • Configuration
    • Package
    • Library / Context
  • Language Constructs
    • Signals, variables, constants
    • Processes und concurrency
    • Control structures
    • Functions / Procedures
    • Generic design descriptions
  • Strong Typing in VHDL
    • Predefined types
    • User defined types
    • Predefined operators
    • Attributes
    • Fixed Point Package 
  • Description Techniques
    • Finite State Machines
    • Memory
  • Testbench Concept
    • Simple Testbenches


  • A stopwatch implemented on an FPGA with Xilinx Vivado

Needed Tools:

  • VHDL tool chain: Xilinx Vivado
  • VHDL-2008 simulator GHDL
  • Waveform viewer: GTKwave
  • Source code editor (e.g. Notepad++)

Anwendbare Technologien

  • VHDL-2008, Vivado, GHDL


  • Grundkenntnisse im Design digitaler Schaltungen
  • Grundkenntnisse zur Benutzung einer Shell


27.02.2023 | Online
Training buchen

Dauer und Kosten

Dauer: 4 Tage (je 4 Stunden)

Kosten: 2.000,00 €
netto pro Teilnehmer inklusive ausführlicher Schulungsunterlagen


Michael Schwarz