VHDL for Simulation - LIVE ONLINE

Programmable logic devices like FPGAs have been established in the daily life. They can be found in mobile phones, IoT devices, cars or cloud data centers. Their area of operation is as broad as their size. FPGAs are used as, but not limited to: protocol adapters, signal converters, or accelerators for video, radar and sensor data processing.

The design of digital circuits in this scale needs a powerful hardware description language which offers different levels of abstraction, so an engineer can create a digital hardware design in a quick and effective way. VHDL fulfills these requirements.

VHDL is a strongly typed hardware description language which prohibits typical programming mistakes in the coding phase. Usually, VHDL is used on the register transfer level (RTL) to design digital circuits of any complexity. Apart from the language constructs for synthesis, VHDL offers a wide range of functionality to describe complex verification models. Thus, it is possible verify digital designs from simple gate up to complicated System-on-Chip (SoC) before going to lab tests.

With recourse to already well-known VHDL language features, this live online training will deepen the knowledge in VHDL and enable the attendee to create simulations with the VHDL testbench concept. The taught language constructs are based on the IEEE Std. 1076-2008 language revision. The theoretical knowledge will be deepened with selected examples and labs on PC.

A basic knowledge in the hardware description language VHDL, e.g. from VHDL for Synthesis is desirable.
 

The theoretical content is supplemented by exercises carried out by the participant.
 

Duration: 4 mornings of 4 hours each

Times:    9.00 a.m. - 11.00 a.m.    Lecture part 1

              11.00 a.m. - 11.15 a.m.  15 minute break

              11.15 a.m. - 1.15 p.m.    Lecture part 2

Exercises: self paced by the participants. Estimated time for completion appr. 2-3 hours. At the end of a lecture, the exercises to be performed by participants are discussed. The results / sample solutions are presented by the trainer the next day.

After registration: the participant receives the presentation documents in electronic form (PDF) as well as the workbook for the exercises, the login data and a list of 
requirements to be done in advanced.

Course Objectives:

Vision: Writing self-checking testbenches in VHDL-2008.

  • Extending VHDL language knowledge
  • Understanding simulation only features of VHDL
  • Understand VHDL simulation execution process
  • Stimuli generation
  • Self-checking testbenches

Agenda:

  • VHDL Flashback
    • Process and concurrency
    • Wait statements, delta cycles
    • Types, operators, attributes
    • Control structures
    • Functions / procedures
    • Generics
  • Testbench Concept
    • Inline Testbenches
    • Modulare Testbenches
    • Code vs. functional Coverage
    • Assertions
  • Test Planung
    • Directed Testing
    • Random Testing
  • Stimuli and Checks
    • Simple stimuli generation
    • Analogue stimuli
    • Random stimuli
    • Timing checks
    • Self-checking testbench
  • File I/O
    • Reading and writing files
    • Logging

Labs

  • Modelling of External Components
    • Example case: UART Git and EDA Tools
  • Needed Tools:
    • VHDL-2008 simulator: GHDL
    • Waveform viewer: GTKwave
    • Source code editor (e.g. Notepad++)

Anwendbare Technologien

  • VHDL-2008, GHDL, GTKwave

Voraussetzungen

  • Grundlegende Kenntnisse über VHDL
  • Grundlagen des VIVADO Design Flows
  • Grundkenntnisse VHDL oder Verilog

Termine


01.12.2020 | Online
Training buchen

Dauer und Kosten


Dauer: 4 Tage (je 4 Stunden)

Kosten: 2.000,00 €
netto pro Teilnehmer inklusive ausführlicher Schulungsunterlagen

Ansprechpartner


Michael Schwarz