Webinar "Understanding Versal: The Adaptable Engines" -jetzt anmelden-

Versal Architecture Essentials - LIVE ONLINE

With Versal, Xilinx offers the first highly integrated chip series in the new ACAP family - Adaptive Compute Acceleration Platform.

The Versal Chips have a heterogeneous architecture with MPSoC, FPGA, PCIe Connectivity, Memory Management, DSP Engines and AI Engines, which in particular enable software and DSP applications to be parallelized and partitioned in hardware to enable the optimal hardware units usage for the specific task.

In this workshop you will be familiarized with the architecture in order to be able to use the building blocks optimally for demanding tasks.

Versal offers multi-processing in SMP and AMP, vector based parallel processing using the AI engines, DSP engines also supporting floating point and as adaptable platform programmable logic (PL) in UltraScale+ technology.

The technical features and optimal use of the components are described in order to compile software and hardware functions on specific hardware units.

There exist many ways of optimization in order achieve better results in performance, power reduction, latency reduction and higher reliability in functional safety.

In particular, function partitioning will be an important aspect here, which requires good knowledge of this architecture.

Network-on-Chip (NoC) provides a hardware bus interfacing which can be configured to get the appropriate throughput and priority management for multi-parallel data transfers on-chip. The Xilinx toolchain Vitis as a unified platform supports multiple entry methods for every type of developer and the essential workflows will be demonstrated.

This online workshop is particularly suitable for system engineers, hardware and software developers in the planning phase of complex tasks, such as acceleration based development in cloud based datacenters or for the edge product.

The theoretical content is supplemented by exercises carried out by the participant.

Duration: 2 mornings of 4 hours each

Times:    9.00 a.m. - 11.00 a.m.    Lecture part 1

              11.00 a.m. - 11.15 a.m.  15 minute break

              11.15 a.m. - 1.15 p.m.    Lecture part 2

Exercises: self paced by the participants. Estimated time for completion appr. 2-3 hours. At the end of a lecture, the exercises to be performed by participants are discussed. The results / sample solutions are presented by the trainer the next day.

After registration: the participant receives the presentation documents in electronic form (PDF) as well as the workbook for the exercises, the login data and a list of 
requirements to be done in advanced.

Course Objectives:

  • Describe the Versal ACAP architecture at a high level
  • Describe the various engines in the Versal ACAP device
  • Use the various blocks from the Versal architecture to create complex systems
  • Describe the memory management using the NoC
  • Perform system-level simulation and debugging
  • Identify and apply different design methodologies


  • Introduction
  • Versal Architecture Overview
  • Design Tool Flow
  • Processing System
  • Boot and Configuration
  • IO, PCIe and Transceivers Resources
  • Clocking Architecture
  • System Interrupts
  • Software Build Flow
  • Network-on-Chip (NoC)
  • Programming Interfaces
  • Application Partitioning
  • Power Management
  • Debugging and Simulation
  • Security Features
  • System Design Methodology


  • Design Tool Flow
  • Boot and Configuration
  • Clocking and IO Resources
  • NoC Introduction and Concepts
  • PCIe Core

Anwendbare Technologien

  • XILINX Versal ACAP


  • Erfahrungen digitaler Systemarchitekturen
  • Kenntnisse im Programmieren mit C/C++
  • Grundkenntnisse der Xilinx FPGA Architektur


13.02.2023 | Online
Training buchen

Dauer und Kosten

Dauer: 2 Tage (je 4 Stunden)

Kosten: 1.000,00 €
netto pro Teilnehmer inklusive ausführlicher Schulungsunterlagen


Michael Schwarz