Bestellen Sie unseren kompletten Trainingskatalog
Trainingkatalog
HomeTrainingDetail

Developing for Mission Critical FPGA & SoC

München / Stuttgart / Freiburg / Frankfurt

FPGA’s and heterogeneous SoC’s are used in an increasing number of mission critical or high reliability applications. These applications span a diverse range from industrial, medical and scientific to defences, transportation and even space. For these devices to safely and reliability operate in an often-harsh environment, a more rigorous design approach is required. One that introduces both stricter engineering governance in the design process and design mitigation techniques.

As such designing these solutions requires the designer to not only understand what techniques can be used at the logic level but also, the wider systematic, regulatory and environmental issues.

This course will therefore present the environmental challenges and what they mean to the logic designer. Along with introducing high level concepts such as SIL level, Reliability and Mean Time to Failure, attendees will also gain an understanding of the importance of engineering governance. The focus of this course is the development of techniques which can be used in programmable logic including Clocking & Reset strategy, Triple Modular Redundancy, IO Planning, Safe State Machines and Counters, Error Correcting Codes, Single Event Effect Mitigation along with Verification strategies and metrics, formal equivalence checking, Synthesis strategies and several other advanced techniques. Each session will complete with a Lab which will demonstrate the concepts outlined in the session. Attendees will at the completion of the course have a detailed understanding of the challenges and strategies to address the creation of mission critical systems for a wide range of applications.


Anwendbare Technologien

These techniques outlined in this course can be applied to any FPGA technology. For reference course XILINX Seven Series devices will be targeted.


Voraussetzungen

It is expected that the attendee is an experienced FPGA designer and has familiarity with electronics and system engineering concepts.

Termine


25.03.2019 in München
24.06.2019 in Stuttgart
02.09.2019 in Freiburg
09.12.2019 in Frankfurt

Dauer und Kosten


Dauer in Tagen: 3Kosten: € 2.100,00 (netto pro Teilnehmer inkl. ausführlichen Schulungsunterlagen sowie Pausengetränken und Mittagessen)

Ansprechpartner


Michael Schwarz

Michael Schwarz

+49 (0) 7664 91313-15
E-Mail schreiben

PLC2 Design

Individuell, detailliert, kundenspezifisch: Mit unserem Expertenwissen erstellen wir für Sie Designs, die genau Ihre Anforderungen erfüllen.

Plc2 Design