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Designing with the Zynq UltraScale+ RFSoC - LIVE ONLINE

PLC2 ONLINE

This course provides an overview of the hard block capabilities for the Zynq® UltraScale+™ RFSoC family with a special emphasis on the RF Data Converter and Soft-Decision FEC blocks.
The focus is on:

  • Describing the RFSoC family in general 
  • Identifying applications for the RF Data Converter and SD-FEC blocks
  • Configuring, simulating, and implementing the blocks
  • Verifying the RF Data Converter on real hardware
  • Reviewing power estimation to help identify the power demands of the RFSoC device in various operating modes
  • Identifying proper layout and PCB considerations since the Zynq UltraScale+ RFSoC is both a high-speed and an analog and digital device

The theoretical content is supplemented by exercises carried out by the participant.
 

Duration: 4 mornings of 4 hours each

Times:    9.00 a.m. - 11.00 a.m.    Lecture part 1

              11.00 a.m. - 11.15 a.m.  15 minute break

              11.15 a.m. - 1.15 p.m.    Lecture part 2

Exercises: self paced by the participants. Estimated time for completion appr. 2-3 hours. At the end of a lecture, the exercises to be performed by participants are discussed. The results / sample solutions are presented by the trainer the next day.

After registration: the participant receives the presentation documents in electronic form (PDF) as well as the workbook for the exercises, the login data and a list of 
requirements to be done in advanced.

Course Objectives:

After completing this comprehensive training, you will have the necessary skills to:

  • Describe in general the new Zynq UltraScale+ RFSoC family
  • Identify typical applications for the RF data converters
  • Describe the architecture and functionality of the RF-ADC
  • Utilize the RF-ADC via configuration, simulation, and implementation
  • Describe the architecture and functionality of the RF-DAC
  • Utilize the RF-DAC via configuration, simulation, and implementation
  • Identify the requirements and options for data converter PCB designs
  • Describe the architecture and functionality of the Soft-Decision FEC hard IP
  • Utilize the Soft-Decision FEC via configuration, simulation, and implementation

Agenda:

  • Introduction
  • Zynq UltraScale+ RFSoC Overview
    • Overview of the Zynq UltraScale+ RFSoC architecture, including brief introductions to RF, RF data converter solutions, SD-FEC solutions, driver support, and tool support. {Lectures, Demo} 
  • RF-ADC Hardware
    • Covers the basics of RF-ADCs. Reviews RF-ADC architecture, functionality, interfaces, configuration, and driver support. {Lectures, Demo, Lab}
  • RF-DAC Hardware
    • Covers the basics of RF-DACs. Reviews RF-DAC architecture, functionality, interfaces, configuration, and driver support. {Lectures, Demo, Lab)
  • RFSoC Hardware
    • Provides an overview of the ZCU111 board and describes board setup. {Lectures}
  • Data Converter Design
    • Describes common features, the design flow, utilizing the example design by simulation and implementation, and verifying RF data converter functionality on real hardware. Includes practice of using a software driver to modify RF data converter parameters. {Lectures, Labs}
  • Data Converter Practice
    • Provides practical RF data converter experience using the ZCU111 board evaluation tool and RF analyzer tool. {Lectures, Practices}
  • PCB Design for RFSoC Devices
    • Describes power requirements, performing power estimation, and utilizing the power design. Analog signal requirements, PCB materials and layer stackup options, and analog trace design are also covered. {Lectures, Demo, Lab}
  • Soft-Decision FEC Hardware
    • Covers the basics of forward error correction. Reviews SD-FEC architecture, functionality, interfaces, configuration, and driver support. {Lectures, Demo, Labs}
  • Summary

Labs

Lab 1: RF Data Converter IP Configuration – Use the Configuration GUI to create instantiation templates (two versions: RF-ADC and RF-DAC).
Lab 2: RF Data Converter Simulation – Simulate the RF Data Converter IP using the IP example design (two versions: RF-ADC and RF-DAC).
Lab 3: RF Data Converter Implementation – Implement a RF Data Converter design and check the functionality on real hardware.
Lab 4: RFSoC Power Estimation – Perform various options to estimate power dissipation for the Zynq® UltraScale+™ RFSoC data converter.
Lab 5: SD-FEC IP Configuration – Use the Configuration GUI to create an instantiation template.
Lab 6: SD-FEC IP Simulation – Simulate the SD-FEC IP using the IP example design.
Note: Some labs and all practices require the ZCU111 board. They will run remotely. All other labs can run locally. 


Anwendbare Technologien

Zynq UltraScale+ RFSoC


Voraussetzungen

Empfohlen: Die Architektur von Zynq UltraScale+ MPSoC verstehen

Vertraut mit Datenkonverter Begriffen und Prinzipien

Vertraut mit "forward errror correction" Begriffen und Prinzipien

Termine


02.11.2020 in PLC2 ONLINE

Dauer und Kosten


Dauer in Tagen: 4Kosten: € 2.000,00 (netto pro Teilnehmer inkl. ausführlichen Schulungsunterlagen sowie Pausengetränken und Mittagessen)

Ansprechpartner


Michael Schwarz

Michael Schwarz

+49 (0) 7664 91313-15
E-Mail schreiben

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