Debugging Multi-Core Designs using Vitis + Cross-Triggered based Debugging using Zynq US+/MPSoC - SHORTIE
Debugging Xilinx MPSoC devices needs different methods like software debugging the processors and hardware debugging the programmable logic units. This shorty will introduce to the concepts Xilinx provides based on the ARM debug architecture to get the essential overview of the system architecture for debug an monitoring support and how this can be used with the Vitis tools when only the standard JTAG access port is used.
Quite useful is a team-based debug method where the software developer and the hardware developer work together and using their known tools like the software debugger for the processors and built in logic analyzers for specific user peripheral modules or AXI bus monitoring. These individual tools need to be synchronized which is called Cross-Debugging here.
We will lead you through the steps of setting up the project to supporting the cross-debugging feature and demonstrate the Vitis environment when we trigger with breakpoints or with signals from the programmable logic side.
This shortie is as recommended for embedded hardware and software developers working with Xilinx SoC/MPSoC or ACAP technologies where these concepts are continued.
Duration: 1 morning of 4 hours each
Times: 9.00 a.m. - 11.00 a.m. Lecture part 1
11.00 a.m. - 11.15 a.m. 15 minute break
11.15 a.m. - 1.15 p.m. Lecture part 2
Timezone: (GMT+02:00) Amsterdam, Berlin, Bern, Rom, Stockholm, Wien
After registration: The participant receives the login data for the shortie after the booking confirmation.
XILINX ZYNQ UltraScale+ MPSoC & RFSoC
Basics of software and hardware debugging