Designing with Xilinx Serial Transceivers - LIVE ONLINE

Learn how to employ serial transceivers in UltraScale™ and UltraScale+™ FPGA designs or Zynq® UltraScale+ MPSoC designs.
The focus is on:
•    Identifying and using the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection
•    Utilizing the Transceivers Wizards to instantiate transceiver primitives
•    Synthesizing and implementing transceiver designs
•    Discussing board design as it relates to the transceivers
•    Testing and debugging

The theoretical content is supplemented by exercises carried out by the participant.
 

Duration: 4 mornings of 4 hours each

Times:    9.00 a.m. - 11.00 a.m.    Lecture part 1

              11.00 a.m. - 11.15 a.m.  15 minute break

              11.15 a.m. - 1.15 p.m.    Lecture part 2

Exercises: self paced by the participants. Estimated time for completion appr. 2-3 hours. At the end of a lecture, the exercises to be performed by participants are discussed. The results / sample solutions are presented by the trainer the next day.

After registration: the participant receives the presentation documents in electronic form (PDF) as well as the workbook for the exercises, the login data and a list of 
requirements to be done in advanced.

Course Objectives:

After completing this comprehensive training, you will have the necessary skills to:

• Describe and use the ports and attributes of the serial transceivers in Xilinx FPGAs and MPSoCs
• Effectively use the following features of the gigabit transceivers:
  • 64B/66B and other encoding/decoding, comma detection, clock correction, and channel bonding
  • Pre-emphasis and receive equalization
• Use the Transceivers Wizards to instantiate GT primitives in a design
• Access appropriate reference material for board design issues involving signal integrity and the power supply, reference clocking, and trace design
• Use the IBERT design to verify transceiver links on real hardware

Agenda:

• Introduction
• UltraScale, UltraScale+, Zynq UltraScale+ Device Transceivers Overview 
• UltraScale, UltraScale+, Zynq UltraScale+ Device Transceivers Clocking and Resets
• Transceiver IP Generation – Transceiver Wizard
• Transceiver Simulation
• PCS Layer General Functionality
• PCS Layer Encoding
• Transceiver Implementation
• PMA Layer Details
• PMA Layer Optimization
• Transceiver Test and Debugging
• Transceiver Board Design Considerations
• Transceiver Application Examples
• Summary

Labs

Lab 1: Transceiver Core Generation – Use the Transceivers Wizard to create instantiation templates.
Lab 2: Transceiver Simulation – Simulate the transceiver IP by using the IP example design.
Lab 3: 64B/66B Encoding – Generate a 64B/66B transceiver core by using the Transceivers Wizard, simulate the design, and analyze the results. 
Lab 4: Transceiver Implementation – Implement the transceiver IP by using the IP example design.
Lab 5: IBERT Design – Verify transceiver links on real hardware.
Lab 6: Transceiver Debugging – Debug transceiver links.
Note: Lab 4, Lab 5, and Lab 6 require a KCU105 board. These labs will run remotely. All other labs can run locally. 

Anwendbare Technologien

• UltraScale Architekturen

Voraussetzungen

• Grundkenntnisse VHDL oder Verilog
• vertraut mit Logikdesign (Zustandsautomaten und synchronem Design)
• Basiswissen der FPGA Architektur und der Xilinx Implementierungswerkzeuge sind hilfreich
• Vertraut mit serial I/O Grundlagen und high-speed serial I/O Standards sind hilfreich