Webinar "Xilinx Versal ACAP - From FPGA to Platform" -jetzt anmelden-

Design, Constraining and Verification of Low Speed and High Speed ADC Interfaces - SHORTIE

The Shortie, which is divided into two parts, describes the procedure for the development, verification and timing specification for two typical representatives from the variety of ADCs offered. 

In the first part, an interface based on the SPI protocol is developed for the ADC AD7476.The AD7476A/AD7477A/AD7478A are 12.bit, 10-bit, and 8- are high speed, low power, successive-approximation analogue-to digital converters (ADCs), respectively. The parts operate from a single 2.35 V to 5.25 V power supply and feature throughput rates up to 1 MSPS. The parts contain a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 13 MHZ. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs.

In the second part, an interface based on Xilinx FPGA ISERDES IP is designed for the ADC AD9252. The AD9252 is an octal, 14-bit, 50 MSPS ADC with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. Operating at a conversion rate of up to 50 MSPS, it is optimized for performance and low power in applications where a small package size is critical.

The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO)  for capturing data on the output and a frame clock (FCO) for signaling a new output byte are provided. 


Duration: 1 morning of 4 hours each

Times:    9.00 a.m. - 11.00 a.m.    Lecture part 1

              11.00 a.m. - 11.15 a.m.  15 minute break

              11.15 a.m. - 1.15 p.m.    Lecture part 2


After booking the recorded Shorties: 

The participant receives the login data for the Shortie after the booking confirmation.

Please note: The link will be available for three weeks. We kindly ask you to keep the link confidential and do not provide it to third parties.

Anwendbare Technologien



  • Basic understanding of digital design techniques. Basic understanding of VHDL for Synthesis and Simulation.


Video on demand | Recorded
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Dauer: 1 Tag (je 4 Stunden)

Kosten: 99,00 €
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Michael Schwarz

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