Webinar "New Features in VHDL-2019" -jetzt anmelden-

Unsere Schulungen - Wissen kompetent vermittelt

Profitieren Sie vom professionellen Know-how unseres E-Teams bei Xilinx-Technologien und Hardwarebeschreibungssprachen: Als Experten mit großer Erfahrung vermitteln Ihnen unsere Teammitglieder die gewünschten Xilinx-Inhalte bzw. Hardwarebeschreibungssprachen gezielt und persönlich.

Unser Programm bietet Inhalte zu Easy Start, Connectivity, FPGA-Technology, Embedded Themen, Vivado, VHDL, Verilog, SystemVerilog, Tcl, Python, DSP, Verifikation und Image Processing. Neben den F2F-Schulungen und Seminaren bieten wir auch Online-Training an. Wählen Sie zwischen einstündigen Webinaren, Shorties und Online Schulungen. Oder wäre unsere Langzeitausbildung etwas für Sie?

Jährlich haben Sie die Wahl aus über 80 Schulungen mit verschiedensten Inhalten. An verschiedenen Standorten in Deutschland oder Inhouse unterrichten Mitglieder unseres Embedded-Teams unter anderem Ingenieure, Techniker, Geschäftsführer, Einkäufer, Projektleiter, Entwickler und Mitarbeiter aus der Verwaltung. Pro Jahr schulen wir dabei rund 1100 Teilnehmer zu Themen der Xilinx-Technologien und von Hardwarebeschreibungssprachen.

Die Länge der Schulungen richtet sich nach den Lerninhalten. Buchen können Sie bei uns ein kostenloses Tagesseminar, einen zwei-/dreitägigen Workshop oder einen fünftägigen Power-Workshop. Möglich sind auch kundenspezifische Schulungen über mehrere Monate. PLC2 bietet darüberhinaus eine Langzeitausbildung für Ihre persönliche Weiterbildung an.

Easy Start

Datum
Titel
Ort
08.12.2020
Easy Start FPGA Vivado - LIVE ONLINE
Online
16.12.2020
Easy Start Embedded for ZYNQ UltraScale+ MPSoC Systems
Freiburg
19.01.2021
Easy Start FPGA Vivado
Freiburg
11.02.2021
Easy Start Embedded for ZYNQ-7000 SoC Systems
Freiburg
01.03.2021
Easy Start Embedded for ZYNQ UltraScale+ MPSoC Systems
Stuttgart
09.03.2021
Easy Start FPGA Vivado
Berlin
10.05.2021
Easy Start Embedded for ZYNQ-7000 SoC Systems
Frankfurt
17.05.2021
Easy Start FPGA Vivado
München
01.07.2021
Easy Start Embedded for ZYNQ UltraScale+ MPSoC Systems
Frankfurt
22.07.2021
Easy Start Embedded for ZYNQ-7000 SoC Systems
München
05.08.2021
Easy Start FPGA Vivado
Stuttgart
04.10.2021
Easy Start Embedded for ZYNQ UltraScale+ MPSoC Systems
Berlin
18.10.2021
Easy Start Embedded for ZYNQ-7000 SoC Systems
Stuttgart
22.11.2021
Easy Start FPGA Vivado
Frankfurt
01.12.2021
Easy Start Embedded for ZYNQ UltraScale+ MPSoC Systems
Freiburg
Auf Anfrage
Easy Start Embedded PetaLinux

FPGA

Datum
Titel
Ort
27.11.2020
New Features in VHDL 2019 - WEBINAR
Online
30.11.2020
Vivado IP Flow - LIVE ONLINE
Online
01.12.2020
Debugging Techniques Using the VIVADO Logic Analyzer
Frankfurt
01.12.2020
bestätigt
Vivado Timing Constraints and Analysis - LIVE ONLINE
Online
01.12.2020
Continuous Integration for EDA Tools - LIVE ONLINE
Online
01.12.2020
VHDL for Simulation - LIVE ONLINE
Online
01.12.2020
Freiburg
04.12.2020
On the development of FPGAs according to DO254 - WEBINAR
Online
07.12.2020
Professional VHDL
Freiburg
10.12.2020
Vivado Logic Analyzer - LIVE ONLINE
Online
14.12.2020
Professional VIVADO
Freiburg
15.12.2020
VHDL for Synthesis - LIVE ONLINE
Online
15.12.2020
Introduction to Verification with OSVVM - LIVE ONLINE
Online
12.01.2021
Git for EDA Tool Flows - LIVE ONLINE
Online
18.01.2021
Dynamic Function eXchange or Partial Reconfiguration
München
21.01.2021
UltraScale/UltraScale+ Architecture - LIVE ONLINE
Online
25.01.2021
Compact FPGA Schaltungstechnik
Freiburg
25.01.2021
Compact VHDL for Synthesis
Berlin
25.01.2021
Vivado Design Flow - LIVE ONLINE
Online
28.01.2021
Compact VHDL for Simulation
Berlin
01.02.2021
Professional VHDL
Freiburg
02.02.2021
Vivado IP Flow - LIVE ONLINE
Online
03.02.2021
Compact Verilog
München
08.02.2021
Professional FPGA
Stuttgart
15.02.2021
Continuous Integration
Stuttgart
16.02.2021
Vivado Timing Constraints and Analysis - LIVE ONLINE
Online
16.02.2021
Continuous Integration for EDA Tools - LIVE ONLINE
Online
16.02.2021
VHDL for Simulation - LIVE ONLINE
Online
16.02.2021
VIVADO Design Suite Tool Flow
Freiburg
17.02.2021
VIVADO Design Suite Static Timing Analysis and XILINX Design Constraints
Freiburg
22.02.2021
Professional FPGA Schaltungstechnik
Freiburg
22.02.2021
SystemVerilog – Advanced Verification for FPGA Design
Frankfurt
22.02.2021
Professional VHDL Testbenches and Verification with OSVVM
Frankfurt
25.02.2021
UVM Made Easy for FPGA Designers
Frankfurt
08.03.2021
Developing for Mission Critical FPGA & SoC
München
11.03.2021
Debugging Techniques Using the VIVADO Logic Analyzer
Berlin
15.03.2021
Compact UltraScale/UltraScale+
München
15.03.2021
Stuttgart
22.03.2021
Professional VIVADO
Freiburg
22.03.2021
Compact VHDL for Synthesis
Freiburg
24.03.2021
Designing with the Spartan-7 Family
Freiburg
25.03.2021
Compact VHDL for Simulation
Freiburg
29.03.2021
Compact VHDL Testbenches and Verification with OSVVM
Stuttgart
08.04.2021
Dynamic Function eXchange or Partial Reconfiguration
Frankfurt
19.04.2021
Professional VHDL
München
19.04.2021
SystemVerilog – Advanced Verification for FPGA Design
München
22.04.2021
UVM Made Easy for FPGA Designers
München
26.04.2021
Professional FPGA Schaltungstechnik
Freiburg
03.05.2021
Compact FPGA Schaltungstechnik
Frankfurt
10.05.2021
Compact VHDL Testbenches and Verification with OSVVM
Freiburg
17.05.2021
Professional FPGA
Frankfurt
17.05.2021
Continuous Integration
Freiburg
26.05.2021
Compact Verilog
Freiburg
07.06.2021
Professional VHDL Testbenches and Verification with OSVVM
Freiburg
07.06.2021
VIVADO Design Suite Tool Flow
Stuttgart
08.06.2021
VIVADO Design Suite Static Timing Analysis and XILINX Design Constraints
Stuttgart
14.06.2021
Debugging Techniques Using the VIVADO Logic Analyzer
Freiburg
15.06.2021
Berlin
16.06.2021
Compact UltraScale/UltraScale+
Freiburg
21.06.2021
Designing with the Spartan-7 Family
Frankfurt
21.06.2021
Compact VHDL for Synthesis
Frankfurt
21.06.2021
Developing for Mission Critical FPGA & SoC
Berlin
24.06.2021
Compact VHDL for Simulation
Frankfurt
12.07.2021
Dynamic Function eXchange or Partial Reconfiguration
Stuttgart
12.07.2021
Professional FPGA Schaltungstechnik
Freiburg
19.07.2021
Professional VIVADO
Freiburg
19.07.2021
Professional FPGA
Freiburg
19.07.2021
Continuous Integration
Frankfurt
26.07.2021
Professional VHDL
Freiburg
26.07.2021
SystemVerilog – Advanced Verification for FPGA Design
Berlin
29.07.2021
UVM Made Easy for FPGA Designers
Berlin
02.08.2021
Compact FPGA Schaltungstechnik
Stuttgart
16.08.2021
Compact VHDL Testbenches and Verification with OSVVM
Berlin
01.09.2021
München
08.09.2021
Compact Verilog
Frankfurt
13.09.2021
Compact VHDL for Synthesis
Stuttgart
16.09.2021
Debugging Techniques Using the VIVADO Logic Analyzer
Stuttgart
16.09.2021
Compact VHDL for Simulation
Stuttgart
20.09.2021
Professional VHDL Testbenches and Verification with OSVVM
Freiburg
20.09.2021
Developing for Mission Critical FPGA & SoC
Freiburg
20.09.2021
VIVADO Design Suite Tool Flow
Frankfurt
21.09.2021
VIVADO Design Suite Static Timing Analysis and XILINX Design Constraints
Frankfurt
29.09.2021
Designing with the Spartan-7 Family
Berlin
29.09.2021
Compact UltraScale/UltraScale+
Frankfurt
04.10.2021
Professional VIVADO
Freiburg
04.10.2021
Compact VHDL Testbenches and Verification with OSVVM
München
11.10.2021
Professional FPGA
München
11.10.2021
SystemVerilog – Advanced Verification for FPGA Design
Freiburg
11.10.2021
Continuous Integration
Berlin
14.10.2021
UVM Made Easy for FPGA Designers
Freiburg
18.10.2021
Professional VHDL
Frankfurt
25.10.2021
Dynamic Function eXchange or Partial Reconfiguration
Freiburg
25.10.2021
Compact FPGA Schaltungstechnik
Berlin
08.11.2021
Professional VHDL Testbenches and Verification with OSVVM
Stuttgart
08.11.2021
VIVADO Design Suite Tool Flow
Berlin
09.11.2021
VIVADO Design Suite Static Timing Analysis and XILINX Design Constraints
Berlin
11.11.2021
Designing with the Spartan-7 Family
Stuttgart
15.11.2021
Professional FPGA Schaltungstechnik
Freiburg
17.11.2021
Compact UltraScale/UltraScale+
Stuttgart
22.11.2021
Compact VHDL for Synthesis
München
25.11.2021
Compact VHDL for Simulation
München
01.12.2021
Compact Verilog
Stuttgart
01.12.2021
Freiburg
01.12.2021
Debugging Techniques Using the VIVADO Logic Analyzer
Frankfurt
06.12.2021
Professional VIVADO
Freiburg
06.12.2021
Developing for Mission Critical FPGA & SoC
Frankfurt
13.12.2021
Professional VHDL
Freiburg
Auf Anfrage
FPGA Designer - Langzeitausbildung
Freiburg
Auf Anfrage
FPGA Power Optimization
Auf Anfrage
Advanced Vivado-Tcl-Scripting
Auf Anfrage
Designing with the XILINX Analog Mixed Signal Solution
Auf Anfrage
SysML-Einführung für Systemingenieure
Auf Anfrage
First-time Right Methods in ASIC and FPGA Design - WEBINAR
Online
Video on demand
Design, Constraining and Verification of Low Speed and High Speed ADC Interfaces - SHORTIE
Recorded

Embedded

Datum
Titel
Ort
01.12.2020
PCI Express Hands-on System Development
Stuttgart
01.12.2020
Zynq UltraScale+ MPSoC for the System Architect - LIVE ONLINE
Online
01.12.2020
AXI Interface Technology
München
03.12.2020
Embedded Design with PetaLinux Tools
München
07.12.2020
Professional Vitis
Berlin
07.12.2020
Compact ZYNQ-7000 SoC for HW Designers
München
08.12.2020
Zynq 7000 SoC for the Hardware Designer - LIVE ONLINE
Online
08.12.2020
Zynq 7000 SoC for the Software Designer - LIVE ONLINE
Online
10.12.2020
ZYNQ UltraScale+ MPSoC System Architecture
München
14.12.2020
Professional ZYNQ UltraScale+ MPSoC
Frankfurt
15.12.2020
Compact Vitis AI
Berlin
21.12.2020
Zynq UltraScale+ MPSoC for the Software Designer - LIVE ONLINE
Online
18.01.2021
Professional ZYNQ-7000 SoC
Freiburg
25.01.2021
Zynq UltraScale+ MPSoC for the Hardware Designer - LIVE ONLINE
Online
25.01.2021
Designing with the Zynq UltraScale+ RFSoC - LIVE ONLINE
Online
25.01.2021
Versal ACAP System Architecture
Freiburg
27.01.2021
Compact Versal ACAP for HW Designers
Freiburg
28.01.2021
Migrating to the Vitis Embedded Software Development - LIVE ONLINE
Online
01.02.2021
Compact Versal ACAP for SW Designers
Stuttgart
08.02.2021
Compact Vitis for Software Designer
Freiburg
08.02.2021
Compact ZYNQ UltraScale+ MPSoC for HW Designers
Frankfurt
10.02.2021
ZYNQ-7000 SoC System Architecture
Frankfurt
11.02.2021
Zynq UltraScale+ MPSoC for the System Architect - LIVE ONLINE
Online
17.02.2021
Compact Vitis for Acceleration
München
22.02.2021
Designing with RF Data Converters
Berlin
22.02.2021
Compact ZYNQ UltraScale+ MPSoC for SW Designers
Stuttgart
25.02.2021
Developing Multimedia Solutions with the VCU and GStreamer
Stuttgart
03.03.2021
Advanced Versal AI Engine
Stuttgart
08.03.2021
PCI Express Hands-on System Development
Freiburg
08.03.2021
Professional ZYNQ UltraScale+ MPSoC
Freiburg
08.03.2021
Compact Vitis AI
Frankfurt
15.03.2021
Compact Python for Embedded
Stuttgart
15.03.2021
Professional Python for Embedded
Stuttgart
15.03.2021
Compact ZYNQ-7000 SoC for HW Designers
Stuttgart
15.03.2021
ZYNQ UltraScale+ MPSoC System Architecture
Stuttgart
15.03.2021
RISC-V Architecture and FPGA Implementation
Freiburg
15.03.2021
Embedded Design with PetaLinux Tools
Stuttgart
15.03.2021
Professional Versal ACAP
München
17.03.2021
Compact ZYNQ-7000 SoC for SW Designers
München
22.03.2021
AXI Interface Technology
Freiburg
22.03.2021
Professional Vitis
Frankfurt
29.03.2021
Advanced ZYNQ Ultrascale+ MPSoC for HW Designers
München
29.03.2021
RISC-V Core Verification and Compliance Testing
Frankfurt
12.04.2021
Expert Versal AI Engine
Freiburg
12.04.2021
Professional ZYNQ-7000 SoC
Freiburg
12.04.2021
Developing Multimedia Solutions with the VCU and GStreamer
Freiburg
26.04.2021
Versal ACAP System Architecture
Frankfurt
28.04.2021
Compact Versal ACAP for HW Designers
Frankfurt
03.05.2021
Compact ZYNQ UltraScale+ MPSoC for SW Designers
Frankfurt
03.05.2021
Designing with RF Data Converters
Freiburg
04.05.2021
Compact Vitis for Acceleration
Berlin
17.05.2021
Compact ZYNQ UltraScale+ MPSoC for HW Designers
Freiburg
17.05.2021
Compact Vitis for Software Designer
Frankfurt
26.05.2021
Compact Versal ACAP for SW Designers
Frankfurt
01.06.2021
ZYNQ-7000 SoC System Architecture
Berlin
01.06.2021
RISC-V Core Verification and Compliance Testing
München
07.06.2021
Professional ZYNQ UltraScale+ MPSoC
Frankfurt
07.06.2021
Compact Vitis AI
Freiburg
08.06.2021
PCI Express Hands-on System Development
Berlin
14.06.2021
Compact Python for Embedded
Freiburg
14.06.2021
Professional Python for Embedded
Freiburg
14.06.2021
Compact ZYNQ-7000 SoC for SW Designers
Berlin
14.06.2021
Compact ZYNQ-7000 SoC for HW Designers
Freiburg
14.06.2021
Advanced ZYNQ Ultrascale+ MPSoC for HW Designers
Berlin
14.06.2021
Professional Versal ACAP
Stuttgart
21.06.2021
ZYNQ UltraScale+ MPSoC System Architecture
Frankfurt
21.06.2021
RISC-V Architecture and FPGA Implementation
Stuttgart
21.06.2021
Professional Vitis
Stuttgart
23.06.2021
bestätigt
Embedded Design with PetaLinux Tools
Frankfurt
28.06.2021
Advanced Versal AI Engine
Frankfurt
28.06.2021
AXI Interface Technology
Frankfurt
12.07.2021
Expert Versal AI Engine
München
14.07.2021
Developing Multimedia Solutions with the VCU and GStreamer
Frankfurt
19.07.2021
Compact Versal ACAP for HW Designers
München
26.07.2021
Professional ZYNQ-7000 SoC
Freiburg
02.08.2021
Professional Vitis
Freiburg
10.08.2021
Compact Versal ACAP for SW Designers
Freiburg
10.08.2021
Compact ZYNQ UltraScale+ MPSoC for SW Designers
Berlin
16.08.2021
Compact Vitis for Acceleration
Freiburg
24.08.2021
Compact ZYNQ UltraScale+ MPSoC for HW Designers
Berlin
30.08.2021
Versal ACAP System Architecture
Stuttgart
01.09.2021
Advanced ZYNQ Ultrascale+ MPSoC for HW Designers
Frankfurt
01.09.2021
Compact Vitis for Software Designer
Berlin
06.09.2021
Compact Python for Embedded
Frankfurt
06.09.2021
Professional Python for Embedded
Frankfurt
06.09.2021
Advanced Versal AI Engine
Freiburg
06.09.2021
RISC-V Core Verification and Compliance Testing
Berlin
09.09.2021
ZYNQ-7000 SoC System Architecture
Freiburg
13.09.2021
Professional ZYNQ UltraScale+ MPSoC
Freiburg
13.09.2021
Compact Vitis AI
Stuttgart
20.09.2021
PCI Express Hands-on System Development
Frankfurt
20.09.2021
Designing with RF Data Converters
Stuttgart
20.09.2021
Professional Versal ACAP
Frankfurt
22.09.2021
Compact ZYNQ-7000 SoC for SW Designers
Freiburg
27.09.2021
Compact ZYNQ-7000 SoC for HW Designers
Frankfurt
27.09.2021
ZYNQ UltraScale+ MPSoC System Architecture
Freiburg
27.09.2021
RISC-V Architecture and FPGA Implementation
Frankfurt
27.09.2021
Embedded Design with PetaLinux Tools
Berlin
27.09.2021
AXI Interface Technology
Berlin
04.10.2021
Developing Multimedia Solutions with the VCU and GStreamer
Berlin
06.10.2021
Compact Versal ACAP for SW Designers
Berlin
18.10.2021
Professional ZYNQ-7000 SoC
Freiburg
20.10.2021
Compact Versal ACAP for HW Designers
Stuttgart
25.10.2021
Expert Versal AI Engine
Frankfurt
02.11.2021
Compact Vitis for Acceleration
Frankfurt
03.11.2021
Compact ZYNQ-7000 SoC for SW Designers
Frankfurt
08.11.2021
Professional Python for Embedded
Berlin
08.11.2021
Compact Python for Embedded
Berlin
08.11.2021
Compact ZYNQ UltraScale+ MPSoC for HW Designers
München
09.11.2021
Versal ACAP System Architecture
München
11.11.2021
ZYNQ-7000 SoC System Architecture
München
15.11.2021
Compact ZYNQ UltraScale+ MPSoC for SW Designers
Freiburg
15.11.2021
Professional Vitis
Berlin
22.11.2021
Professional Versal ACAP
Freiburg
29.11.2021
AXI Interface Technology
München
29.11.2021
Embedded Design with PetaLinux Tools
München
01.12.2021
Advanced ZYNQ Ultrascale+ MPSoC for HW Designers
Stuttgart
01.12.2021
RISC-V Architecture and FPGA Implementation
München
06.12.2021
ZYNQ UltraScale+ MPSoC System Architecture
München
06.12.2021
Compact ZYNQ-7000 SoC for HW Designers
München
06.12.2021
PCI Express Hands-on System Development
Stuttgart
08.12.2021
Compact Vitis for Software Designer
München
13.12.2021
RISC-V Core Verification and Compliance Testing
Stuttgart
13.12.2021
Professional ZYNQ UltraScale+ MPSoC
Frankfurt
13.12.2021
Designing with RF Data Converters
München
13.12.2021
Compact Vitis AI
Berlin
20.12.2021
Advanced Versal AI Engine
München
Auf Anfrage
Essentials of Microprocessors
Auf Anfrage
Auf Anfrage
High-Speed Ethernet – Hands-On System Development
Auf Anfrage
Embedded Linux Development with Yocto Project
Auf Anfrage
Embedded Linux Treiberentwicklung
Auf Anfrage
Professional MicroBlaze System Design
Auf Anfrage
Debug your Linux – Praktisches Debuggen auf echter Hardware
Auf Anfrage
FPGA Designer Embedded - Langzeitausbildung
Freiburg
Auf Anfrage
Real-Time Control System Development using RTOS
Video on demand
Running Multiple OS using XEN Hypervisior for Zynq US+ MPSoC - WEBINAR
Online

DSP & Image Processing

Datum
Titel
Ort
01.12.2020
Advanced VIVADO HLS
München
07.12.2020
Expert DSP Design using System Generator
Berlin
18.01.2021
Vivado High-Level-Synthese for Hardware Designers - LIVE ONLINE
Online
01.02.2021
DSP Design using System Generator
München
01.02.2021
Expert DSP Design using System Generator
München
04.02.2021
Model Composer
München
16.02.2021
Frankfurt
19.04.2021
DSP Design using System Generator
Frankfurt
19.04.2021
Expert DSP Design using System Generator
Frankfurt
22.04.2021
Model Composer
Frankfurt
10.05.2021
Freiburg
02.08.2021
Stuttgart
06.09.2021
DSP Design using System Generator
Freiburg
06.09.2021
Expert DSP Design using System Generator
Freiburg
09.09.2021
Model Composer
Freiburg
22.11.2021
München
06.12.2021
Expert DSP Design using System Generator
Berlin
06.12.2021
DSP Design using System Generator
Berlin
09.12.2021
Model Composer
Berlin

Connectivity

Datum
Titel
Ort
01.12.2020
DDR4 Interfacing with XILINX FPGAs
Stuttgart
07.12.2020
Designing with Xilinx Serial Transceivers - LIVE ONLINE
Online
14.12.2020
Designing with PCI Express
Berlin
14.01.2021
PCIe Protocol Overview - LIVE ONLINE
Online
18.01.2021
Signal Integrity
Frankfurt
20.01.2021
Designing with Ethernet MAC Controllers
München
21.01.2021
FPGA Board-Design
Frankfurt
25.01.2021
Designing an Integrated PCI Express System PCIe Gen3 - LIVE ONLINE
Online
26.01.2021
Designing with Multi-Gigabit Serial I/O
München
02.02.2021
ZYNQ – Board Design and High Speed Interfacing
Frankfurt
08.02.2021
DDR4 Interfacing with XILINX FPGAs
Berlin
17.02.2021
Designing with PCI Express
Stuttgart
08.03.2021
UltraScale FPGAs – Connectivity
München
15.03.2021
High-Speed Memory Interfacing
Berlin
22.03.2021
VERSAL ACAP Connectivity (3 Tage)
Frankfurt
22.03.2021
VERSAL ACAP Connectivity (5 Tage)
Frankfurt
19.04.2021
Professional PCI Express
Berlin
10.05.2021
Designing with Multi-Gigabit Serial I/O
Berlin
17.05.2021
Designing with PCI Express
Freiburg
20.05.2021
Designing with Ethernet MAC Controllers
Stuttgart
26.05.2021
ZYNQ – Board Design and High Speed Interfacing
München
07.06.2021
Signal Integrity
Berlin
10.06.2021
FPGA Board-Design
Berlin
14.06.2021
High-Speed Memory Interfacing
München
12.07.2021
VERSAL ACAP Connectivity (3 Tage)
Berlin
12.07.2021
VERSAL ACAP Connectivity (5 Tage)
Berlin
19.07.2021
DDR4 Interfacing with XILINX FPGAs
Frankfurt
26.07.2021
UltraScale FPGAs – Connectivity
Frankfurt
02.08.2021
Professional PCI Express
Frankfurt
01.09.2021
Designing with Multi-Gigabit Serial I/O
Frankfurt
06.09.2021
Designing with PCI Express
München
13.09.2021
ZYNQ – Board Design and High Speed Interfacing
Berlin
29.09.2021
Designing with Ethernet MAC Controllers
Berlin
04.10.2021
UltraScale FPGAs – Connectivity
Berlin
02.11.2021
High-Speed Memory Interfacing
Frankfurt
08.11.2021
Professional PCI Express
Freiburg
15.11.2021
Signal Integrity
Stuttgart
18.11.2021
Designing with Ethernet MAC Controllers
Frankfurt
18.11.2021
FPGA Board-Design
Stuttgart
22.11.2021
VERSAL ACAP Connectivity (3 Tage)
Stuttgart
22.11.2021
VERSAL ACAP Connectivity (5 Tage)
Stuttgart
01.12.2021
DDR4 Interfacing with XILINX FPGAs
Stuttgart
06.12.2021
Designing with PCI Express
Berlin

Online Training

Datum
Titel
Ort
27.11.2020
New Features in VHDL 2019 - WEBINAR
Online
30.11.2020
Vivado IP Flow - LIVE ONLINE
Online
01.12.2020
bestätigt
Vivado Timing Constraints and Analysis - LIVE ONLINE
Online
01.12.2020
Continuous Integration for EDA Tools - LIVE ONLINE
Online
01.12.2020
VHDL for Simulation - LIVE ONLINE
Online
01.12.2020
Zynq UltraScale+ MPSoC for the System Architect - LIVE ONLINE
Online
04.12.2020
On the development of FPGAs according to DO254 - WEBINAR
Online
07.12.2020
Designing with Xilinx Serial Transceivers - LIVE ONLINE
Online
08.12.2020
Zynq 7000 SoC for the Hardware Designer - LIVE ONLINE
Online
08.12.2020
Easy Start FPGA Vivado - LIVE ONLINE
Online
08.12.2020
Zynq 7000 SoC for the Software Designer - LIVE ONLINE
Online
10.12.2020
Vivado Logic Analyzer - LIVE ONLINE
Online
15.12.2020
VHDL for Synthesis - LIVE ONLINE
Online
15.12.2020
Introduction to Verification with OSVVM - LIVE ONLINE
Online
21.12.2020
Zynq UltraScale+ MPSoC for the Software Designer - LIVE ONLINE
Online
12.01.2021
Git for EDA Tool Flows - LIVE ONLINE
Online
14.01.2021
PCIe Protocol Overview - LIVE ONLINE
Online
18.01.2021
Vivado High-Level-Synthese for Hardware Designers - LIVE ONLINE
Online
21.01.2021
UltraScale/UltraScale+ Architecture - LIVE ONLINE
Online
25.01.2021
Zynq UltraScale+ MPSoC for the Hardware Designer - LIVE ONLINE
Online
25.01.2021
Designing with the Zynq UltraScale+ RFSoC - LIVE ONLINE
Online
25.01.2021
Designing an Integrated PCI Express System PCIe Gen3 - LIVE ONLINE
Online
25.01.2021
Vivado Design Flow - LIVE ONLINE
Online
28.01.2021
Migrating to the Vitis Embedded Software Development - LIVE ONLINE
Online
02.02.2021
Vivado IP Flow - LIVE ONLINE
Online
11.02.2021
Zynq UltraScale+ MPSoC for the System Architect - LIVE ONLINE
Online
16.02.2021
Vivado Timing Constraints and Analysis - LIVE ONLINE
Online
16.02.2021
Continuous Integration for EDA Tools - LIVE ONLINE
Online
16.02.2021
VHDL for Simulation - LIVE ONLINE
Online
Auf Anfrage
First-time Right Methods in ASIC and FPGA Design - WEBINAR
Online
Video on demand
Design, Constraining and Verification of Low Speed and High Speed ADC Interfaces - SHORTIE
Recorded
Video on demand
Running Multiple OS using XEN Hypervisior for Zynq US+ MPSoC - WEBINAR
Online

Seminare

Datum
Titel
Ort
30.03.2021
FPGA Design Technik - PLC2
Freiburg
13.04.2021
Schaltungssynthese mit VHDL - PLC2
Stuttgart
06.05.2021
Schaltungssimulation mit VHDL - PLC2
München
28.09.2021
FPGA Design Technik - PLC2
Frankfurt
19.10.2021
Schaltungssynthese mit VHDL - PLC2
München
09.11.2021
Schaltungssimulation mit VHDL - PLC2
Frankfurt

Berufsbegleitende Weiterbildung

PLC2 bildet Ingenieure und Techniker weiter zu FPGA Experten.  Unser strukturiertes Ausbildungsprogramm vermittelt das Know-how für den gesamten Entwicklungsprozess.

Sie haben die Wahl zwischen zwei zertifizierten Weiterbildungen:

Bei Interesse kontaktieren Sie uns bitte. Wir geben Ihnen gerne genauere Informationen zu unserer Weiterbildung. 

Ansprechpartner


Michael Schwarz
Training & Organisation