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Zynq UltraScale+ MPSoC for the Hardware Designer - LIVE ONLINE


This course provides software designers with an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC family  from a hardware architectural perspective. The FPGA based HDL programming extends the capabilities of the PS while several AXI based interconnects are provided with different types. Also booting and hardware bring-up topics are discussed.

The theoretical content is supplemented by exercises carried out by the participant.

Duration: 3 mornings of 4 hours each

Times:    9.00 a.m. - 11.00 a.m.    Lecture part 1

              11.00 a.m. - 11.15 a.m.  15 minute break

              11.15 a.m. - 1.15 p.m.    Lecture part 2

Exercises: self paced by the participants. Estimated time for completion appr. 2-3 hours. At the end of a lecture, the exercises to be performed by participants are discussed. The results / sample solutions are presented by the trainer the next day.

After registration: the participant receives the presentation documents in electronic form (PDF) as well as the workbook for the exercises, the login data and a list of 
requirements to be done in advanced.

Course Objectives:

  • Identifying the key elements of the processing units APU, RPU, PMU
  • Reviewing the various power domains and their control structure
  • Illustrating the processing system (PS) and programmable logic (PL) connectivity
  • Managing AXI Interfacing
  • Utilizing QEMU to emulate hardware behavior


  • Zynq UltraScale+ MPSoC ARM APU Unit
  • Zynq UltraScale+ MPSoC ARM RPU Unit
  • Hardware-Software Virtualization
  • QEMU for Application Devlopment and Debugging
  • Boot Concepts
  • First Stage Boot Loader
  • System Protection
  • Clocks and Resets
  • AXI Interconnects and Traffic Generator
  • The Platform Management Unit PMU
  • Power Management


  • Exploring the Architecture of the Zynq UltraScale+ MPSoC
  • Boot and Configuration
  • Bare-Metal Application Development and Debugging
  • Exploring AXI Performance
  • Managing Power for Other Processors

usable technology



Conceptual understanding of embedded processing systems

Basics in working with the Vivado tool suite

FPGA HDL programming experience


19.08.2020 in PLC2 ONLINE

Duration and Cost

Duartion in days: 3Costs:: € 1.500,00 netto per participant incl. documents


Michael Schwarz

Michael Schwarz

+49 (0) 7664 91313-15


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