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Zynq 7000 SoC for the Hardware Designer - LIVE ONLINE

PLC2 ONLINE

This online course introduces you to building the hardware platform for the Zynq 7000 SoC. It also iterates on the Xilinx Vivado toolchain. You will learn how to configure the processing system  (PS) and strategies to deploy the programmable logic to enhance the already large base of IPs provided there. The AXI components and capabilities are introduced. The basic concepts of software development with SDK are taught to provide understanding into HW and SW interaction with focus on bring up, simulation and debugging.

Practical implementation tips and best practices are also provided throughout to enable you to make good design decisions and keep your design cycles to a minimum.

The theoretical content is supplemented by exercises carried out by the participant.
 

Duration: 3 mornings of 4 hours each

Times:    9.00 a.m. - 11.00 a.m.    Lecture part 1

              11.00 a.m. - 11.15 a.m.  15 minute break

              11.15 a.m. - 1.15 p.m.    Lecture part 2

Exercises: self paced by the participants. Estimated time for completion appr. 2-3 hours. At the end of a lecture, the exercises to be performed by participants are discussed. The results / sample solutions are presented by the trainer the next day.

After registration: the participant receives the presentation documents in electronic form (PDF) as well as the workbook for the exercises, the login data and a list of 
requirements to be done in advanced.

Course Objectives:

  • Describe the various tools that encompass a Xilinx embedded design
  • Rapidly architect an embedded system containing Single / Dual Cortex A9 or MicroBlaze processor using the Vivado IP integrator and Customization Wizard
  • Develop software applications utilizing the Eclipse-based Software Development Kit (SDK)
  • Create and integrate an IP-based processing system component in the Vivado Design Suite
  • Design and add a custom AXI interface-based peripheral to the embedded processing system
  • Simulate a custom AXI interface-based peripheral using verification IP (VIP)

Agenda:

  • Embedded UltraFast Design Methodology

  • Overview of Embedded Hardware Development

  • Driving the IP Integrator Tool

  • Overview of Embedded Software Development

  • Driving the SDK Tool

  • AXI: Introduction

  • AXI: Variations and Transaction

  • Introduction to Interrupts

  • Interrupts: Hardware Architecture and Support

  • Creating a New AXI IP with the Wizard

  • AXI: BFM Simulation Using Verification IP

  • MicroBlaze Processor Architecture Overview

  • Zynq-7000 SoC Architecture Overview

Labs

  • Driving the IP Integrator Tool
  • Driving the SDK Tool
  • Exploring AXI Transactions Using the AXI Traffic Generator
  • Building Custom AXI IP
  • Introduction to Verification IP Simulation
  • Exploring the Architecture of the MicroBlaze Processor
  • Exploring the Architecture of the Zynq-7000 SoC

Needed Tools

  • Xilinx Vivado Design or System Edition 2019.1
  • Zynq 7000 Dev Kit (Zed Board)

usable technology

XILINX ZYNQ-7000 SoC Family

Zynq 7000 System on a programmable Chip


requirements

FPGA design experience

Basic knowledge of the C programming language

Conceptual understanding of microprocessors

Some HDL modeling experience

Dates


03.08.2020 in PLC2 ONLINE

Duration and Cost


Duartion in days: 3Costs:: € 1.500,00 netto per participant incl. documents

Contact


Michael Schwarz

Michael Schwarz

+49 (0) 7664 91313-15
E-Mail

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