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Xilinx SDSoC/SDAccel/HLS to Vitis - Silica

PLC2 ONLINE

New programming methods are offered for FPGA and SoC technologies, which also enable software developers to program hardware without having to master hardware programming languages. SDx tools from XILINX addresses the software developer and these methods will get a new and improved concept with Vitis. The online seminar gives you an overview of these tools and shows in which applications and platforms the various tools can be used. The elementary tool High-Level-Synthesis (HLS) offers language support for C/C ++ and System-C and can generate optimized hardware code. The SDSoC tool is used for Zynq SoC/MPSoC technologies to move the sequential processor code to the programmable logic for acceleration purpose. SDAccel can be used for all XILINX FPGA devices in order to use an OpenCL kernel to program a XILINX hardware platform for server or computer based hardware accelerators. And with Vitis, Xilinx has recently combined these acceleration tools presented here in a freely available software framework to set a new standard that makes it easier now for the SW developer to access many methods of hardware acceleration.

Finally, we show you a Vivado generated Zynq MPSoC PS/PL design imported to the Vitis development environment. This seminar helps you to better understand the new concepts of Xilinx tools for software developers.

 

Times:    9.00 a.m. - 10.30 a.m.    Lecture part 1

              10.30 a.m. - 11.00 a.m.  30 minute break

              11.00 a.m. - 12.30 p.m.    Lecture part 2

 

Duration and Cost:

  • Duration: half a day (2x 90 min.)
  • This seminar is free of charge
  • The seminar language is English

 

Agenda: 

  • High-Level-Synthesis (HLS) Overview

  • XILINX SDx Tools Overview

  • The XILINX SDSoC Tool

  • The XILINX SDAccel Tool

  • Vitis Unified Software Platform

  • Vitis Embedded Software Development

  • Vitis Acceleration Libraries

  • XILINX Devices and Platforms for Vitis


usable technology

FPGA technologies

Zynq SoCs, MPSoC & RFSoCs

ACAP Versal

ACAP Alveo


requirements

Fundamentals of Embedded Systems

Comfort with the C/C++ programming language

Basic knowledge of FPGA technology

Dates


on request in PLC2 ONLINE

Duration and Cost


Duartion in days: 1Costs:: € 0,00 netto per participant incl. documents

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