XILINX Partial ReconfigurationFreiburg
This course demonstrates how to use the Vivado® Design Suite to construct, implement, and download a Partially Reconfigurable (PR) FPGA design.
You will gain a firm understanding of PR technology and learn how successful PR designs are completed. You will also identify best design practices and understand the subtleties of the PR design flow.
This course covers both the tool flow and mechanics of successfully creating a PR design. It also describes several techniques focusing on appropriate coding styles for a PR system as well as system-level design considerations and practical applications.
The PR design approach allows strategies for non-realtime multiplexing hardware functions by exchanging partial bitstream configuration files. This is an advanced methodology for in-system-programming FPGA devices.
XILINX FPGAs, SoC, MPSoC & RFSoC
Basic knowledge of FPGA technology
Basic knowledge of the VHDL or Verilog programming languages
Basic knowledge of the Vivado design flow
recommended: knowledge of microprocessors