Vivado IP Flow - LIVE ONLINEPLC2 ONLINE
The Xilinx® Vivado® Design Suite provides an intellectual property (IP) centric design flow that lets you add IP modules to your design from various design sources. Central to the environment is an extensible IP catalog that contains Xilinx-delivered Plug-and-Play IP. Vivado IP Flow address usage of IPs in either Project or Non-Project modes by referencing the created Xilinx core delivered by the IP catalog. The participants will learn how to define their own IPs by packaging complete designs using the Vivado IP packager tool. Vivado IP Flow also coverst he design of komplex IP based (sub)systems using the IP integrator tool.
The theoretical content is supplemented by exercises carried out by the participant.
Duration: 3 mornings of 4 hours each
Times: 9.00 a.m. - 11.00 a.m. Lecture part 1
11.00 a.m. - 11.15 a.m. 15 minute break
11.15 a.m. - 1.15 p.m. Lecture part 2
Exercises: self paced by the participants. Estimated time for completion appr. 2-3 hours. At the end of a lecture, the exercises to be performed by participants are discussed. The results / sample solutions are presented by the trainer the next day.
After registration: the participant receives the presentation documents in electronic form (PDF) as well as the workbook for the exercises, the login data and a list of
requirements to be done in advanced.
- Introduction to the Vivado IP Flow
- Designing custom IPs
- Using IP Integrator
- Vivado IP Flow
- Creating and Packaging Custom IP
- Using an IP Container
- Designing with IP Integrator
- Managing Remote IP
All kind of FPGA technologies
Basic knowledge in VHDL or Verilog