Since the invention of FPGAs, the development methodology was continuously evolving from schematic entry towards RTL based system modeling A downside of these methods is the requirement, that not only the desired functionality itself but also the structure of the hardware such as pipelining, latency, data throughput or area limitations have to be taken into account and designed for. This new way, named HLS (High Level Synthesis) gives the freedom to the FPGA developer to concentrate on the more abstract system modeling aspects without having to care about implementation specific details of the hardware structure. Using ‘C’, ‘C++’ and ‘SystemC’ as a programming language, Vivado™ HLS automates the implementation and optimization by transforming the ‘C’-based model into a RTL one.
The significant advantages for verification and implementation provided by this new method are obvious: It allows, for example, to take a ‘C’-based algorithm, optimize it for speed, latency, area etc. and quickly compare the results. The widely used ‘C’-level verification additionally allows early detection of design errors. Hence, both advantages contribute to shorten tremendously the development time of FPGA projects and simultaneously increasing the quality of results.
Grundlagenwissen in VHDL / Verilog sind von Vorteil
Grundlagenwissen in C-Sprachen sind von Vorteil