VIVADO Design Suite Static Timing Analysis and XILINX Design ConstraintsFrankfurt / Berlin
The Vivado™ Design Suite is a new and highly integrated design environment explicitly created for handling huge, system oriented programmable designs. The main pillars are a unified and scalable data base allowing great cross probing possibilities and a unique test environment for a shortened learning curve. In addition, increased adherence to industry standards such as AMBA® AXI4, IP-XACT (for meta data for self developed IP cells), Tool Command Language (Tcl), Synopsys® Design Constraints (SDC) etc. allows for easy scalability and a simplified automation of the development process. Vivado™ is conceptually designed in a way to deal with all aspects (logic, SW, I/O, mixed signal, etc.) of programmable technology and this for designs of a complexity of up to 100M ASIC gates.
This class discusses in a detailed way the creation of XDC constraints (Xilinx Design Constraints) and the static timing analysis. On top of that, proper usage of FPGA resources is discussed along with how the unified Vivado™ design database can be used efficiently for e.g. analysis purposes.
7 Series and UltraScale FPGAs
Solid knowledge in digital design techniques
Knowledge of FPGA technology, Vivado software flow and basic constraining
Working experience with VHDL or Verilog