UVM Made Easy for FPGA DesignersFrankfurt / Berlin / Freiburg
Today’s FPGA designs have become complex SoC type of designs which has driven the complexity to a level that used to be specific to ASICs some years in the past. For a complete verification of those systems, writing testbenches has become a challenging task. Different verification methodologies have addressed this on different levels. The most comprehensive approach is the Universal Verification Methodology, UVM. It has become a standard (IEEE 1800.2-2017). It provides SystemVerilog Verification base components that can be used to create a testbench infrastructure with a high reuse potential.
Since the UVM library is very complex building a testbench from scratch is a time-consuming task and requires a good knowledge of the tools the library provides. In order to help verification engineers to build a testbench infrastructure very quickly UVM Framework has been developed. With UVM Framework a UVM testbench can be created very rapidly and with a few changes the testbench is ready for simulation within a few hours.
The workshop UVM MADE EASY FOR FPGA DESIGNER will introduce to the most important UVM building blocks to provide a basic understanding how a UVM testbench looks like, how the component instance creation process works and how the verification components communicate with each other and the DUT.
- FPGA design or verification engineers
- Verification – Approaches and Methodologies
- UVM - Fundamentals and Principles
- UVM framework – Library components, structure and API
Knowledge of SystemVerilog and OOP concepts are advantageous