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UltraScale/UltraScale+ Architecture - LIVE ONLINE

PLC2 ONLINE / PLC2 ONLINE

The UltraScale/UltraScale+ online training describes the hardware architecture of these devices. After a general introduction oft he ASML architecture the workshop focus on adetailled descriptions of the internal architectural blocks like RAMs (Distributed RAMs, BRAMs, ULTRA_RAMS) as well as Clock buffers, Slices and IOs.

The theoretical content is supplemented by exercises carried out by the participant.

Duration: 2 mornings of 4 hours each

Times:    9.00 a.m. - 11.00 a.m.    Lecture part 1

              11.00 a.m. - 11.15 a.m.  15 minute break

              11.15 a.m. - 1.15 p.m.     Lecture part 2

Exercises: self paced by the participants. Estimated time for completion appr. 2-3 hours. At the end of a lecture, the exercises to be performed by participants are discussed. The results / sample solutions are presented by the trainer the next day.

After registration: the participant receives the presentation documents in electronic form (PDF) as well as the workbook for the exercises, the login data and a list of 
requirements to be done in advanced.

Agenda:

  • UltraScale Architecture Clocking Resources
  • UltraScale Architecture Block RAM Memory Resources
  • UltraScale Architecture FIFO Memory Resources
  • UltraRAM Memory
  • DDR4 Design Creation Using MIG
  • UltraScale Architecture I/O Resources Overview

 


usable technology

UltraScale/UltraScale+ Technologies


requirements

Basic knowledge in VHDL

Basic knowledge in digital design techniques

Basic knowledge of XILINX Design Tool Flow

Dates


18.06.2020 in PLC2 ONLINE
21.07.2020 in PLC2 ONLINE

Duration and Cost


Duartion in days: 2Costs:: € 1.000,00 netto per participant incl. documents

Contact


Michael Schwarz

Michael Schwarz

+49 (0) 7664 91313-15
E-Mail

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