Developing complex FPGAs with demanding timing standardsoften requires procedures such as floorplanning, Relationally Placed Macros (RPM), and incremental design, but with special Time-driven implementation procedures (timing constraints).The 2-day PLC2 workshop “Timing Constraints” concentrates on such timing constraints and is aimed at FPGA designers who already have a sound basic knowledge of Xilinx FPGA development. after the detailed presentation of the TRACE tool used for Static Timing Analysis typical timing errors and their cause will be analyzed. In addition to this, participant will learn the methods to correct these errors. Based on the “Timing Closure” strategy developed by Xilinx total available bandwidth of existing timing constraints will be presented.
The next topic discusses the Global timing constraints on the simple and synchronous circuits. Next we will see the definition of complex paths like multicycle constraints, false path in general circuits. Furthermore there is also a possibility to enter these timing constraints using Xilinx Constraints Editor basically this is an effective method of entering the Timing Specification in the UCF file. Third day is optional for hands on labs.
All Xilinx FPGA Technologies including 7-Series FPGAs, ISE Design System
Detailed knowledge of the ISE design system