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Signal Integrity


The new XILINX FPGA families allow interfaces with high clock and data rates, in which the developer is forced to allow for the effects of signal integrity. The 3-day PLC2 workshop “Signal Integrity for XILINX FPGAs” is aimed at developers who want to implement high-speed interfaces between a XILINX FPGA and other components.
Participants are taught to judge when the signal integrity needs to be taken into account. For further analysis, IBIS models, for example, are available, the use and creation of which is described. These models form the basis for advanced analyses (reflections, crosstalk, etc.) with HyperLynx.
Based on these basic analyses, participants learn how to simulate complex interfaces, for example DDR3 / DDR4 memory interfacing. The simulation of the serial interfaces is based on various design kits, whose design-specific adaptation is shown with a lab.

usable technology

Current FPGA/SoC/MPSoC technologies


Basic knowledge of circuit technology and usage of Windows based tools


16.11.2020 in Stuttgart

Duration and Cost

Duartion in days: 3Costs:: € 2.100,00 netto per participant incl. documents


Michael Schwarz

Michael Schwarz

+49 (0) 7664 91313-15


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PLC2 Design

Flexible, dynamic, individual: Your specific design project determines our workflow.

Plc2 Design

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