The Vivado™ Design Suite is a new and highly integrated design environment explicitly created for handling huge, system oriented programmable designs. The main pillars are a unified and scalable database allowing great cross probing possibilities and a unique test environment for a shortened learning curve. In addition, increased adherence to industry standards such as AMBA® AXI4, IPXACT (for meta data for self developed IP cells), Tool Command Language (Tcl), Synopsys® Design Constraints (SDC) etc. allows for easy scalability and a simplified automation of the development process. Vivado™ is conceptually designed in a way to deal with all aspects (logic, SW, I/O, mixed signal, etc.) of programmable technology and this for designs of a complexity of up to 100M ASIC gates.
This class gives a thorough introduction into this new development environment reaching from first steps through more advanced techniques to constraining with XDC (XILINX Design Constraints – based on SDC) and the associated timing analysis.
Basic knowledge in VHDL or Verilog
Solid knowledge of digital design techniques
Knowledge of the FPGA technology