The new XILINX Zynq UltraScale+ RFSoC devices allow very fast RF data converter interfaces.
This 5-day course combines a deep discussion of both, hard- and software aspects to design with RFSoC devices.
This course starts a deep discussion of the architecture and functionality of the RF data converters. You will learn how to utilize the RF data converter by configuration, simulation and implementation.
The RF design at PCB level is very challenging. In this course, you will learn the PCB level design requirements. The realization options for a successful PCB design will be discussed deeply.
Additionally, this course describes the architecture and functionality of the SD-FEC hard IP.
The processing system discussion starts with an overview followed by deep discussions of the ARM architectures such as APU and RPU and the XILINX extensions such as the PMU as well. A lot of labs allow the participant to configure the processing system and to simulate applications.
Additionally, this course tackles system specific features such as system protection and clock and reset structures as well. An important lesson describes the memory configuration with multi-port management, QoS, and the required AXI interfaces to manage the high bandwidths of the RF-ADC/DAC.
Zynq UltraScale+ RFSoC
Basic familiarity with data converter terms and principles
Basic knowledge on Zynq UltraScale+ MPSoC hardware and software design
Basic familiarity with forward error correction terms and principles