Introduction to Verification with OSVVM - LIVE ONLINEPLC2 ONLINE
Today’s FPGA and ASIC designs have drastically increased in size and complexity since the very beginning of digital hardware design. These elaborate circuits are described as a hierarchy of sub-systems in hardware description languages like VHDL. The subsystems are most likely connected by standardized bus infrastructures like AXI, Avalon or WishBone. In addition, these system might add a soft CPU IP core or an embedded ARM CPU core. Such a design is way too complex to verify it with simple, assertion-based testbenches.
With Open Source VHDL Verification Methodology (OSVVM) a structured approach is given, that increases the reusability of testbench code. OSVVM is a free and open source available VHDL library that offers packages, data types, subprograms and algorithms that are needed in almost every testbench. OSVVM is offering a methodology that comprises the following topics: transaction-based modeling (TBM), self-checking, scoreboards, memory modeling, functional coverage, directed, algorithmic and constrained random as well as intelligent testbench test generation.
This 4-days online training starts with simple testbenches and progressively increases the level of abstraction. Along the way students learn about: subprogram usage, libraries, file reading and writing, modeling issues, transaction-based testbenches, bus functional models, transaction-based models, record types, resolution functions, abstractions for interface connectivity, model synchronization methods, protected types, access types (pointers), data structures (e.g. scoreboards), directed, algorithmic, constrained random, and coverage driven random test generation, self-checking (result, timing, protocol checking and error injection), functional coverage, representation of analog values and periodic waveforms, timing and execution of code, test planning, and configurations.
The theoretical content is supplemented by exercises carried out by the participant.
Duration: 4 mornings of 4 hours each
Times: 9.00 a.m. - 11.00 a.m. Lecture part 1
11.00 a.m. - 11.15 a.m. 15 minute break
11.15 a.m. - 1.15 p.m. Lecture part 2
Exercises: self paced by the participants. Estimated time for completion appr. 2-3 hours. At the end of a lecture, the exercises to be performed by participants are discussed. The results / sample solutions are presented by the trainer the next day.
After registration: The participant receives the presentation documents in electronic form (PDF) as well as the workbook for the exercises, the login data and a list of
requirements to be done in advanced.
Vision: Learn to write reusable testbenches for automated tests prepared for Continuous Integration
- Understand the OSVVM methodology
- Writing self-checking testbenches
- Code reuse and abstraction of testbench components
- Data and test pattern randomization
- Functional coverage
- From Basics to subprograms
- Transaction-based models (TBM / BFM)
- Elements of a transaction-based model
- Creating tests
- Constrained random testing
- Functional coverage
A UART model and simplified x86 CPU bus interface
- VHDL-2008 simulator: ModelSim/QuestaSim, Active-HDL/Riviera-PRO or GHDL + GTKwave
- Source code editor (e.g. Notepad++, Sigasi Studio)
Advanced knowledge in VHDL and digital circuit design (e.g. PLC2 online classes: VHDL for Synthesis and VHDL for Simulation)