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High-Speed Memory Interfacing

Berlin / Munich / Frankfurt

The new Xilinx FPGA platforms allow for very fast interfaces to external memories. They have new IOBs inside the them and optimised wizards are used to generate the memory controller. This results in a shift of implementation challenges from the FPGA to the board level. The very high data rates require special care in the board design domain.
The 3-day workshop “High-Speed Memory Interfacing” targets to FPGA designers, as well as to System Architects and PCB layout designers, who want to implement and operate fast memory interfaces.
This workshop explains the features of the IOBs for memory interfaces. As a result of this, the students learn how to efficiently use these features in interaction with the PCB design. Solutions for signal integrity problems will be discussed. In particular signal quality and timing issues are discussed exhaustively.
Based on evaluation boards with practical design and verification examples are demonstrated. Simulation options get also shown. Moreover, rules for successful realisation of memory interfaces will be commented on.


usable technology

XILINX 7 Series FPGAs

Spartan-6

Virtex- 6 FPGAs


requirements

Basic knowledge on VHDL and FPGA implementation

Grundlegende Kenntnisse über FPGA-Implementierung

Dates


16.03.2020 in Berlin
03.06.2020 in Munich
24.11.2020 in Frankfurt

Duration and Cost


Duartion in days: 3Costs:: € 2.100,00 netto per participant incl. documents

Contact


Michael Schwarz

Michael Schwarz

+49 (0) 7664 91313-15
E-Mail

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