With the availability of the various Xilinx FPGA families, both FPGA designers and layout Developers are faced with new implementation possibilities and challenges. All kinds of interfaces to External components enable a variety of application areas. The high clock rates accompanying the components require a comprehensive knowledge of physical design in the FPGA environment.
The 2-day PLC2 workshop “Xilinx FPGA Board Design” trains designers in the practical use of Xilinx FPGAs.
It is aimed not only at VDHL developers who also have to integrate physical Interfaces of the FPGA, but also at design engineers and PCB layouters. The content covers the partly conflicting design restrictions of both design teams in order to show methods for effective Implementation of customer projects. Based on the FPGA power requirements (basics and power estimator), power-supply solutions (AC/DC or DC/DC converters, filtering and decoupling) are presented. The termination required for high clock or data rates is covered in detail, taking into account different signal levels and termination variants. A special section deals with clock-pulse supply (strategies and implementation) and the connection to high-speed components on the board. Rules of PCB design (PCB tracing, layer stacking) are also explained.
Grundkenntnisse Schaltungstechnik und Umgang mit Windows-Programmen