Designing with Multi-Gigabit Serial I/OBerlin / Berlin / Frankfurt
The new Xilinx FPGA platforms allow serial interfaces up to the 30 Gbit/s range. This involves the use of new transceivers, which require extensive know-how for quick and effective use.
The target audience of the 3-day PLC2 workshop “Designing with Multi-Gigabit Serial I/O” are developers wishing to implement serial interfaces in the range of Gbit/s.
This workshop enables designers to effectively use all available features of the serial transceivers, define the interfaces and attributes necessary for using the features, and instantiate the serial transceiver primitives available with the Architecture Wizard which is integral part of the IP Catalog.
This allows to implement project-specific or standardised serial interfaces. The IBERT Design for ChipScope is used to show an effective verification of the serial transmission link. Signal-integrity topics, including a simulation example and pointers on board design provide practical tips for implementation.
XILINX 7 Series FPGAs
Virtex- 6 FPGAs
Basic knowledge on VHDL and FPGA implementation
Grundlegende Kenntnisse über FPGA-Implementierung