Order our complete trainingcatalog
Trainingkatalog
HomeTrainingDetails

Designing with Multi-Gigabit Serial I/O

Berlin / Berlin / Frankfurt

The new Xilinx FPGA platforms allow serial interfaces up to the 30 Gbit/s range. This involves the use of new transceivers, which require extensive know-how for quick and effective use.
The target audience of the 3-day PLC2 workshop “Designing with Multi-Gigabit Serial I/O” are developers wishing to implement serial interfaces in the range of Gbit/s.
This workshop enables designers to effectively use all available features of the serial transceivers, define the interfaces and attributes necessary for using the features, and instantiate the serial transceiver primitives available with the Architecture Wizard which is integral part of the IP Catalog.
This allows to implement project-specific or standardised serial interfaces. The IBERT Design for ChipScope is used to show an effective verification of the serial transmission link. Signal-integrity topics, including a simulation example and pointers on board design provide practical tips for implementation.


usable technology

XILINX 7 Series FPGAs

Spartan-6

Virtex- 6 FPGAs


requirements

Basic knowledge on VHDL and FPGA implementation

Grundlegende Kenntnisse über FPGA-Implementierung

Dates


18.02.2019 in Berlin
27.05.2019 in Berlin
02.09.2019 in Frankfurt

Duration and Cost


Duartion in days: 3Costs:: € 2.100,00 netto per participant incl. documents

Contact


Michael Schwarz

Michael Schwarz

+49 (0) 7664 91313-15
E-Mail

Downloads


Download as Flyer

PLC2 Design

Flexible, dynamic, individual: Your specific design project determines our workflow.

Plc2 Design

more trainings