Design, Constraining and Verification of Low Speed and High Speed DAC Interfaces - SHORTIEPLC2 ONLINE
This shortie describes the procedure for the development, verification and timing specification for a typical SPI based DAC Interface.
The AD7303 is a dual, 8-bit voltage out DAC that operates from a single +2.7 V to +5.5 V supply. Its on-chip precision output buffers allow the DAC outputs to swing rail to rail. This device uses a versatile 3-wire serial interface that operates at clock rates up to 30 MHz, and is compatible with QSPI, SPI, microwire and digital signal processor interface standards. The serial input register is sixteen bits wide; 8 bits act as data bits for the DACs, and the remaining eight bits make up a control register.
The on-chip control register is used to address the relevant DAC, to power down the complete device or an individual DAC, to select internal or external reference and to provide a synchronous loading facility for simultaneous update of the DAC outputs with a software LDAC function. The low power consumption of this part makes it ideally suited to portable battery operated equipment.
AD7303 will receive its 8 bits of information from the system board through 16 clock cycles with first eight bits consisting of eight control bits and the remaining eight bits representing the 8 bits of the data with the MSB first. Each bit is received by the rising edge of the serial clock line. The function dictated by the first eight control bits is executed when the chip select line is brought high.
Duration: 1 morning of 4 hours each
Times: 9.00 a.m. - 11.00 a.m. Lecture part 1
11.00 a.m. - 11.15 a.m. 15 minute break
11.15 a.m. - 1.15 p.m. Lecture part 2
After registration: The participant receives the login data for the shortie after the booking confirmation.
Basic understanding of digital design techniques. Basic understanding of VHDL for Synthesis and Simulation.