Debugging Techniques Using the VIVADO Logic AnalyzerBerlin / Freiburg / Stuttgart / Frankfurt
With the ever increasing integration density of today’s FPGAs, the number of access points for measurements are on a decline. Thus verifying the real functionality is becoming more and more difficult.
Amongst the main reasons for an FPGA internal logic analysis tool are the small number of user I/Os compared to the internal connections, cost and the integration level of the PCB. The former ChipScope Pro tool is now fully integrated in the Vivado Tool Suite. This provides the possibility of FPGA internal logic analysis along with different configurations of the trigger unit and data storage options, to ideally fit the requirements of the measurement task.
Even HDL novices may take advantage of this alternative verification mechanism. It may complement (or replace extensive) HDL simulations when bringing new systems into service.
One of the important points for the implementation is, that despite the additional functionality, the original real time requirement still need to be met.
During the exercises, the debug cores get created for real designs based on a provided evaluation board.
The attendee learns how the software of the logic analyser is structured and in which way commonly known functions such as trigger menu and waveform representation of the captured data are available. Since processor internal bus signals are synchronised to the debugging tool and the retrieved data may be displayed in parallel, this tool is of particular interest for embedded controller applications. Additionally, this verification method allows to accelerate HDL based simulations through the possibility of probing data in hardware and exporting the results for file I/O usage during the next simulation.
This class shows all important features necessary to master even demanding FPGA verification scenarios.
Advanced knowledge on XILINX FPGA architectures
Basic knowledge in VHDL