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DDR4 Interfacing with XILINX FPGAs

Stuttgart / Berlin / Frankfurt / Stuttgart

The new Xilinx UltraScale families allow very fast interfaces to external memories based on new and improved structures on silicon and a new memory wizard as well.
Realization challenges are shifting from chip level to board level with the new UltraScale families. The very high data rates required extreme accuracy in PCB design.
The 3-day workshop “DDR4 Interfacing with Xilinx FPGAs” targets to hardware designers, as well as to System Architects and Layout designers, who want to implement DDR4 interfaces in a system successfully. This workshop starts with a comparison between DDR3 and DDR4 memories. The DDR4 enhancements are discussed together with the new features and operational details of DDR4 memories.
All design steps are described: DDR4 design generation, functional simulation, and implementation. The design will be tested on real hardware. Special focus is on physical layer – signal integrity. Parameters for signal quality and timing are covered.
Practical design and verification examples are discussed. Simulation options on PCB level are described and demonstrated during labs. The participants will learn how to derive design rules for PCB design. Methodical tips and tricks complete the content.


usable technology

UltraScale FPGAs

MPSoC Familien


requirements

Basic knowledge on VHDL and FPGA implementation

Grundlegende Kenntnisse über FPGA-Implementierung

Dates


09.12.2019 in Stuttgart
17.02.2020 in Berlin
01.07.2020 in Frankfurt
01.12.2020 in Stuttgart

Duration and Cost


Duartion in days: 3Costs:: € 2.100,00 netto per participant incl. documents

Contact


Michael Schwarz

Michael Schwarz

+49 (0) 7664 91313-15
E-Mail

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