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Continuous Integration

Stuttgart / Freiburg / Frankfurt / Berlin

Agile and collaborative software development flows are gaining popularity as they result in more builds, tests, and integrations as well as faster delivery and deployment. Hence the code is in a “release-at-anytime” state, the scratch/issue-to-production time is drastically reduced. Hardware and embedded system designers who also have software background understand the need for such development style in the area of electronics hardware design. However, agile development is not available in EDA environments due to lack of software support. In this workshop, a complete set-up to create agile and collaborative workflow for small and midsized design teams is presented.
There are three fundamental objectives of the workshop: Firstly, it is aimed that the attendees will have a deep understanding and ability to use a version control system (Git) at the end of the course. Secondly, they will be capable of creating an agile and collaborative workflow in GitLab. This includes, that the attendees will comprehend how to increase the code quality with the use of code reviews. Finally, VUnit and OSVVM Verification IPs are explained to transition from assertion-based testbenches to a fully automated regression testing environment, that integrates into the Git workflows.
To achieve these goals, an assertion-based VHDL testbench example is given to the attendees as a core of the course’s practice. A transformation is presented that incorporates Verification IPs from OSVVM in order to increase the reuse of testbench code.
All tools and services used in this workshop are well known and well tested such as cloud services. They enable ubiquitous access to the users. Moreover, these services can be installed in a protected intranet environment to provide full security control to the IT department, while utilizing state-of-the-art tools to the development teams. VHDL coding and how to create assertion-based VHDL testbenches are not parts of this workshop. Attendees should be confident in understanding and writing VHDL testbenches as well as using VHDL simulators.


usable technology

none


requirements

Advanced knowledge in VHDL and assertion-based VHDL testbenches

Basic knowledge in Python or any other scripting language

Dates


17.02.2020 in Stuttgart
04.05.2020 in Freiburg
20.07.2020 in Frankfurt
26.10.2020 in Berlin

Duration and Cost


Duartion in days: 5Costs:: € 3.100,00 netto per participant incl. documents

Contact


Michael Schwarz

Michael Schwarz

+49 (0) 7664 91313-15
E-Mail

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