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Compact ZYNQ UltraScale+ MPSoC for HW Designers

Freiburg / Stuttgart / Munich

This three-days course provides both the tool- and architecture- specific aspects necessary for development with the XILINX ZYNQ UltraScale + MPSoC device.
At the beginning, special attention will be paid to the Embedded Design Flow.
The focus in this course is on embedded hardware development with the XILINX VIVADO tool using the IP-Integrator, which also covers software development with the XILINX SDK.
Then the overall architecture of the ZYNQ UltraScale + MPSoC Processing System (PS) is discussed.
For the connection of AXI-based IPs in the Programmable Logic (PL) to the Processing System (PS), it is essential to understand the AXI protocol as well as the Interrupt structures.
The final section of this course consists of creating and verifying custom IP cores with an AXI based interface port to the Processing System.


usable technology

XILINX ZYNQ UltraScale+ MPSoC & RFSoC


requirements

Verständnis digitaler Systemarchitekturen

VHDL und FPGA Kenntnisse sind von Vorteil

Grundlagen Programmiersprache C ist von Vorteil

Dates


06.05.2019 in Freiburg
18.09.2019 in Stuttgart
25.11.2019 in Munich

Duration and Cost


Duartion in days: 3Costs:: € 2.100,00 netto per participant incl. documents

Contact


Michael Schwarz

Michael Schwarz

+49 (0) 7664 91313-15
E-Mail

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