Compact UltraScale/UltraScale+Munich / Freiburg / Frankfurt / Stuttgart
The PLC2 workshop “Compact UltraScale ” teaches the first-time or recurring user in the way, the FPGA building blocks of the XILINX UltraScale FPGAs work and how they can be used most effectively. The emphasis of this workshop is put on the thorough discussion of the common architectural building blocks of the UltraScale devices. After an overview, detailed explanations are given to the functional blocks such as e.g. configurable logic blocks (CLB), I/O blocks (IOB), DSP etc. In addition to that, it will be explained how to migrate a 7-Series design to UltraScale architecture. Due to its crucial role in an FPGA design, special attention is given to the clocking resources and clock structure. To top the content off, dedicated hardware resources (such as e.g. GTX, GTY and PCIe) will briefly be introduced.
Moreover, suitable coding techniques get explained throughout the class to allow synthesis to produce the best possible implementation results based on the target device’s resources. Exercises help to reinforce the learning process. Nor the underlying commands of hardware description languages like VHDL nor global implementation strategies for FPGA designs are covered in this class.
Please refer to PLC2 workshops like “Compact VHDL” or “Professional VHDL”.
Basic knowledge in VHDL
Basic knowledge in digital design techniques
Basic knowledge of XILINX Design Tool Flow