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ZYNQ UltraScale+ MPSoC System Architecture

The 2-day workshop will focus on the system architecture of the XILINX Zynq UltraScale+ MPSoC devices.
Starting with the general overview of this technology the next topics showing the details of the hardware architecture and use cases of the Processing System (PS).
Especially the power management with the Platform Management Unit (PMU) in the PS is a new feature of the ZYNQ MPSoC architecture which enables customizable watchdogs and dynamic power optimization.
With several sharing memory ressources the user can configure its access in PS and PL via AXI ports with supported hardware coherency management. As next system-specific features such as System Protection and clock and reset structures discussed.
The DDRAM Controller enables multiple port arbitration, priorization, flow control, and class traffics like Video stream storage.
The boot and configuration process of the Zynq Ultra- Scale+ MPSoC components are discussed in detail. During the individual chapters various exercises, which are carried out independently by the participants, will be provided.

Applicable technologies

  • XILINX ZYNQ UltraScale+ MPSoC & RFSoC


  • Good understanding of digital embedded systems
  • Basic knowledge of the programming language C


23.03.2023 | Stuttgart
01.06.2023 | Frankfurt

Duration & Fee

Duration: 2 days

Fee: 1,500.00 €
net per person including detailed training material, beverages during breaks and lunch


Michael Schwarz