Xilinx Versal ACAP - From FPGA to Platform - WEBINAR
With the Versal ACAP Family Xilinx introduces a completely new architecture that allows to efficiently deploy a wide range of heterogenous computation resource.
This Webinar describes the core concepts of the device family and introduces the computation engines, the APU (Arm A72) and the RPUs. As evolution to the MPSoC, the Versal family exhibits a hardened platform that allows to bind further acceleration engines to these CPUs with predictable performance. The architecture knowledge is used to generate a platform in Vivado and a short outlook into the acceleration kernel design with Vitis is given.
Register for this webinar for free.
If the date does not suit you, you still have the possibility to watch this webinar. The webinar will be recorded and available "on demand" afterwards.
During the webinar you have time to ask questions directly to the trainer.
The course language is English.
- XILINX Versal ACAP
- FPGA technologies