Vivado Timing Constraints and Analysis - LIVE ONLINE
The PLC2 online training Vivado Timing Constraints and Analysis trains the participant in the specification and application of timing requirements (Timing Constraints) for the FPGA design.
Timing constraints are restrictions on the timings of events. A system with real-time constraints is called a real-time system. Not merely the performance of such systems, but also their feasibility depends on the satisfaction of real-time constraints. Timing constraints are used to specify the timing characteristics of the design. Timing constraints may affect all internal timing interconnections, delays through logic (LUTs) and between flip-flops, registers or RAMs. Timing constraints can be either global or path-specific. From timing perspective, the designer creates timing constraints for synthesis and physical implementation (Layout) which are a series of constraints applied to a given set of paths or nets that dictate the desired performance of a design. Constraints may be period, frequency, net skew, maximum delay between end points, or maximum net delay. After synthesis or implementation the performances achieved is analysed using the Vivado Static Timing Analysis tool.
Static Timing Analysis is a method for determining if a circuit meets timing constraints without having to simulate so it is much faster than timing-driven, gate-level simulation. The Vivado STA tools check setup, hold and multicycle constraints, clock gating constraints, maximum frequency and many other design rules. Static Timing Analysis accept synthesized design netlist as well as physical design netlist. Xilinx specific timing libraries as well as extracted or estimated delay information and user defined timing constraints act as inputs to perform static timing analysis.
The theoretical content is supplemented by exercises carried out by the participant.
Duration: 4 mornings of 4 hours each
Times: 9.00 a.m. - 11.00 a.m. Lecture part 1
11.00 a.m. - 11.15 a.m. 15 minute break
11.15 a.m. - 1.15 p.m. Lecture part 2
Exercises: self paced by the participants. Estimated time for completion appr. 2-3 hours. At the end of a lecture, the exercises to be performed by participants are discussed. The results / sample solutions are presented by the trainer the next day.
After registration: the participant receives the presentation documents in electronic form (PDF) as well as the workbook for the exercises, the login data and a list of
requirements to be done in advanced.
- Introduction to Vivado Timing Constraints XDC
- Basic Timing Constraints
- IO Timing Constraints
- Introduction to Vivado Static Timing Analysis
- Timing Constraints Wizard
- Timing Constraint Editor
- Introduction to Clock Constraints
- IO Constraints and Virtual Clocks
- Setup and Hold Timing Analysis
- Generated Clocks
- Clock Group Constraints
- Introduction to Timing Exceptions
- Timing Summary Report
- Timing Simulation
- IO Timing Scenarios
- Source-Synchronous IO Timing
- System-Synchronous IO Timing
- Timing Constraints Priority
Lab1: Timing Constraint Wizard
Lab2 Introduction to Clock Constraints
Lab3: IO Constraints and Virtual Clocks
Lab4: Introduction to Timing Exceptions
Lab5: Source-Synchronous IO Timing
- Basic knowledge in VHDL or Verilog
- Basic knowledge of the VIVADO Design Flow