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Vivado Logic Analyzer - LIVE ONLINE

With the ever increasing integration density of today’s FPGAs, the number of access points for measurements are on a decline. Thus verifying the real functionality is becoming more and more difficult. Amongst the main reasons for an FPGA internal logic analysis tool are the small number of user I/Os compared to the internal connections, cost and the integration level of the PCB. The former ChipScope Pro tool is now fully integrated in the Vivado Tool Suite. This provides the possibility of FPGA internal logic analysis along with different configurations of the trigger unit and data storage options, to ideally fit the requirements of the measurement task.

The theoretical content is supplemented by exercises carried out by the participant.

Duration: 2 mornings of 4 hours each

Times:    9.00 a.m. - 11.00 a.m.    Lecture part 1

              11.00 a.m. - 11.15 a.m.  15 minute break

              11.15 a.m. - 1.15 p.m.    Lecture part 2

Exercises: self paced by the participants. Estimated time for completion appr. 2-3 hours. At the end of a lecture, the exercises to be performed by participants are discussed. The results / sample solutions are presented by the trainer the next day.

After registration: the participant receives the presentation documents in electronic form (PDF) as well as the workbook for the exercises, the login data and a list of 
requirements to be done in advanced.

Course Objectives:

  • Introduction tot he Vivado Hardware debugger
    • Describe what the Vivado logic analyzer (VLA) is
  • Enumerate the benefits of the Vivado logic analyzer
  • Explain the basic probing flows to debug your design
  • Describe the trigger mechanism of the Vivado logic analyzer
    • Explain how to use the Run trigger option
  • Display captured data using the Waveform view
  • Describe the ILA core and its properties
  • Describe VIO and IBERT core usage
  • Describe what the debug core hub is and why it is used
  • Describe debug core hub insertion and customization
  • Identify the different debug cores that can be added directly to HDL sources
  • Describe how to customize, instantiate, and connect debug cores in the design
  • Explain the steps involved in HDL instantiation debug probing flow


  • Introduction to the Vivado Logic Analyzer  
  • Introduction to Triggering 
  • Debug Cores  
  • HDL Instantiation Debug Probing Flow  
  • Netlist Insertion Debug Probing Flow  
  • JTAG to AXI Master Core  
  • Debug Flow in an IP Integrator Block Design  
  • Remote Debugging Using the Vivado Logic Analyzer  
  • Trigger Using the Trigger State Machine in the Vivado Logic Analyzer Vivado Design Suite Debug Methodology 
  • Trigger and Debug at Device Startup  
  • Debugging the Design Using Tcl Commands


Lab1: HDL Instantiation Flow

Lab2:  Netlist Insertion Flow

Lab3:  Debug Flow in an IP Integrator Block Design 

Lab4:  Remote Debugging Using the Vivado Logic Analyzer 

Lab5: Trigger Using the Trigger State Machine in the Vivado Logic Analyzer

Applicable technologies

  • 7 Series FPGAs and newer devices


  • Basic knowledge of the VIVADO Design Flow
  • Intermediate VHDL or Verilog knowledge


30.03.2023 | Online
12.06.2023 | Online

Duration & Fee

Duration: 2 days (4 hours each)

Fee: 1,000.00 €
net per person including detailed training material


Michael Schwarz

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