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VIVADO HLS

Since the invention of FPGAs, the development methodology was continuously evolving from schematic entry towards RTL based system modeling A downside of these methods is the requirement, that not only the desired functionality itself but also the structure of the hardware such as pipelining, latency, data throughput or area limitations have to be taken into account and designed for. This new way, named HLS (High Level Synthesis) gives the freedom to the FPGA developer to concentrate on the more abstract system modeling aspects without having to care about implementation specific details of the hardware structure. Using ‘C’, ‘C++’ and ‘SystemC’ as a programming language, Vivado™ HLS automates the implementation and optimization by transforming the ‘C’-based model into a RTL one.
The significant advantages for verification and implementation provided by this new method are obvious: It allows, for example, to take a ‘C’-based algorithm, optimize it for speed, latency, area etc. and quickly compare the results. The widely used ‘C’-level verification additionally allows early detection of design errors. Hence, both advantages contribute to shorten tremendously the development time of FPGA projects and simultaneously increasing the quality of results.


Applicable technologies

  • XILINX FPGA and ZYNQ families

Requirements

  • Basic knowledge in C languages beneficial
  • Basic knowledge in VHDL or Verilog beneficial

Dates


10.05.2021 | Freiburg
Booking
02.08.2021 | Stuttgart
Booking
22.11.2021 | Munich
Booking

Duration & Fee


Duration: 3 days

Fee: 2,100.00 €
net per person including detailed training material, beverages during breaks and lunch

Contact


Michael Schwarz

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