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Vitis HLS – Getting Started - LIVE ONLINE

This Online training describes the methodology of C/C++ based programming and to synthesize these as modules in the programmable logic of Zynq or FPGA devices.

The productivity of development can be significantly improved with the Vitis integral HLS tool including acceleration libraries and provides optimized capabilities for algorithm development. Optimized VHDL or Verilog code is generated by the tool for the Vivado compilation, and so the development effort for many modules can be reduced. The web seminar is aimed at hardware/software developers who have not yet worked with the Xilinx HLS to show you how to use the tool and what type of modules are suitable for C / C ++ synthesis and thus as an alternative to HDL coding.

The theoretical content is supplemented by exercises carried out by the participant.
 

Duration: 2 mornings of 4 hours each

Times:    9.00 a.m. - 11.00 a.m.    Lecture part 1

              11.00 a.m. - 11.15 a.m.  15 minute break

              11.15 a.m. - 1.15 p.m.    Lecture part 2

Exercises: self paced by the participants. Estimated time for completion appr. 2-3 hours. At the end of a lecture, the exercises to be performed by participants are discussed. The results / sample solutions are presented by the trainer the next day.

After registration: the participant receives the presentation documents in electronic form (PDF) as well as the workbook for the exercises, the login data and a list of 
requirements to be done in advanced.

Course Objectives:

  • Understanding the concept and methodology of Vitis HLS
  • Describe the Vitis HLS Design flow
  • Identify the steps to extract RTL from C
  • Describe the architecture optimization and analyze methods
  • Describe the integration of HLS modules in the Vivado project

Agenda:

  • Introduction to High-Level-Synthesis
  • Introduction to the Vivado HLS Tool Flow
  • Performance and Utilization Exploration
  • Directive usage for optimization
  • IO Interface Methodology
  • The HLS UltraFast design methodology
  • Interfacing HLS modules with HDL modules
  • C/C++-Coding and provided DSP Libraries
  • Optimization for Performance PIPELINE and DATAFLOW
  • Optimizing Structures for Performance
  • Improving Area and Resource Utilization
  • HLS Tool C Libraries
  • HLx Design Flow – System Integration

Applicable technologies

  • Xilinx FPGAs, Zynq SoC, Zynq UltraScale+ MPSoC and RFSoC, Versal

Requirements

  • Basic Knowledge of the Xilinx FPGA development
  • Basic knowledge in Digital Signal Processing
  • Comfort with the C/C++ programming language

Dates


17.01.2022 | Online
Booking

Duration & Fee


Duration: 2 days (4 hours each)

Fee: 1,000.00 €
net per person including detailed training material

Contact


Michael Schwarz