Webinar "Versal ACAP: The processing system interfaces" -register now-

Vitis Tools for Acceleration - Creating a RTL Kernel: from HDL to reusable packaged Kernel - WEBINAR

The Webinar will review the acceleration design flow with the Xilinx Vitis tools. While the high level design entry methods range from HLS to Model Composer there is provision for re-using RTL Modules within this design flow as well.  This is the main target of the presentation and will explain the dependencies and steps to take to seamlessly fit legacy RTL code into acceleration design flows.

 

Registration:

Register for this webinar for free.

Date:

If the date does not suit you, you still have the possibility to watch this webinar. The webinar will be recorded and available "on demand" afterwards.

Live:

During the webinar you have time to ask questions directly to the trainer.

Material:

As a live participant you will receive a complete list of all answered questions during the webinar after the event.

Language:

The course language is English.


Applicable technologies

  • Vitis unified software environment

Requirements

  • none

Dates


Video on demand | Online
Booking

Duration & Fee


Duration: 1 hour

Fee: 0.00 €
PLC2 FREE LIVE WEBINAR

Contact


Michael Schwarz