Vitis Tools for Acceleration – Creating a RTL Kernel - WEBINAR

The application acceleration on Alveo™ cards allows to describe function accelerators in HLS. If legacy implementations in RTL are considered, the toolflow can also account for these to be reused. These RTL descriptions need to be mapped to support a certain set of interfaces that are required in the Vitis™ Acceleration flow.

This presentation describes these interfaces and explains the relation of the interfaces to the acceleration toolflow to build a proper connectivity and to satisfy the runtime environment with flow control features. We will describe the packaging process from RTL level to IP component to obtain a reusable component. This then is wrapped into a kernel that can finally be integrated into a Vitis system level build to achieve application acceleration on an Alveo platform.

 

Registration:

Register for this webinar for free.

Date:

If the date does not suit you, you still have the possibility to watch this webinar. The webinar will be recorded and available "on demand" afterwards.

Live:

During the webinar you have time to ask questions directly to the trainer.

Language:

The course language is English.


Applicable technologies

  • FPGA technologies
  • Acceleration and AI
  • Vitis unified software platform

Requirements

  • none

Dates


on request

Duration & Fee


Duration: 1 Stunde

Fee: 0.00 €
PLC2 FREE LIVE WEBINAR

Contact


Michael Schwarz