Webinar "Xilinx Versal ACAP - Creating a Custom Embedded Platform" -register now-

Vitis Acceleration Methodology - LIVE ONLINE

The Vitis™ unified software platform tool combines all aspects of Xilinx® software development and for acceleration purpose this includes the embedded software development flow for the processors and the hardware development flow for specific function calls selected for offloading to hardware.

In this online session you will learn the methodology and development processes in the context of Linux based embedded processing on Xilinx Zynq technology.

The acceleration modules need to be defined as kernel modules and can be developed using C/C++, OpenCL C, or RTL.

Software/hardware engineers and application developers can benefit from the Vitis™ unified software environment when using the OpenCL framework with support for the acceleration flow.

This workshop is valuable for embedded developers using a Zynq SoC/MPSoC device.

The theoretical content is supplemented by exercises carried out by the participant.
 

Duration: 2 mornings of 4 hours each

Times:    9.00 a.m. - 11.00 a.m.    Lecture part 1

              11.00 a.m. - 11.15 a.m.  15 minute break

              11.15 a.m. - 1.15 p.m.    Lecture part 2

Exercises: self paced by the participants. Estimated time for completion appr. 2-3 hours. At the end of a lecture, the exercises to be performed by participants are discussed. The results / sample solutions are presented by the trainer the next day.

After registration: the participant receives the presentation documents in electronic form (PDF) as well as the workbook for the exercises, the login data and a list of 
requirements to be done in advanced.

Course Objectives:

  • Describe how the FPGA architecture lends itself to parallel computing
  • Explain how the Vitis™ software environment helps software developers to focus on applications
  • Describe and analyze the OpenCL API memory model
  • Create kernels from C, C++, or RTL IP using the RTL Kernel Wizard
  • Apply kernel optimization techniques
  • Move data efficiently between kernel and global memory
  • Profile the design using the Vitis™ analyzer tool

Agenda:

  • Course Introduction                                      
  • Introduction to the Vitis Unified Software Platform                 
  • Vitis IDE Tool Flow                                                 
  • Introduction to Hardware Acceleration                               
  • Vitis Execution Model and XRT                                        
  • Synchronization Techniques                                                    
  • Profiling Analysis                                                          
  • Debugging                                                           
  • Introduction to C-C++ based Kernel Optimization                                 
  • Using the RTL Kernel Wizard to Reuse Existing IP as Accelerators    
  • Optimization Methodology                                            
  • Introduction C/C++-based Kernel Optimization                                       
  • Vitis Software Accelerated Libraries                                
  • System Design Methodology

Labs:

  • Vitis IDE Tool Overview
  • Vitis Execution Model and XRT
  • Synchronizing the Design
  • Introduction to C-C++ based Kernels
  • Using the RTL Kernel Wizard to build the IP as Accelerators
  • Optimizing the Performance of a Design

Applicable technologies

  • Zynq SoCs, MPSoC & RFSoCs
  • XILINX Versal ACAP

Requirements

  • Basic knowledge of FPGA architectures
  • Comfort with the C/C++ programming language
  • Knowledge of embedded system development

Dates


21.06.2021 | Online
Booking
19.07.2021 | Online
Booking

Duration & Fee


Duration: 2 days (4 hours each)

Fee: 1,000.00 €
net per person including detailed training material

Contact


Michael Schwarz