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Versal ACAP: The processing system interfaces - WEBINAR

With the Versal ACAP familiy many elements are an evolution from the Zynq Ultrascale+ MPSoC devices. This session will cover the SoC features to provide insight into the full width of peripherals and connectivity in the processing system (or now CIPS) of these devices offer. Furthermore, the interconnects to other regions of the devices are described to give insight into the capabilities of the ACAP technology and hint on variability of systems built on these.

 

Registrierung:

Melden Sie sich kostenlos für dieses Webinar an. 

Live:

Sie haben während des Webinars Zeit direkt Fragen an den Trainer zu stellen.

Sprache:

Die Kurssprache ist englisch.


Applicable technologies

  • Acceleration and AI
  • FPGA technologies
  • XILINX Versal ACAP

Requirements

  • none

Dates


Video on demand | Online
Booking

Duration & Fee


Duration: 1 hour

Fee: 0.00 €
PLC2 FREE LIVE WEBINAR

Contact


Michael Schwarz

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