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VERSAL ACAP Connectivity (3 days)

The XILINX VERSAL Adaptive Compute Acceleration Platform (ACAP) allows very fast interfaces to external components based on significantly improved silicon structures as well as new IP Core configuration wizards. Realization challenges are shifting from chip level to board level with the new VERSAL platform. Extreme accuracy in PCB design is mandatory to achieve high-speed data rates.
The 3-day Workshop“VERSAL ACAP – Connectivity” has been developed for hardware designers, system architects and layout designers who want to successfully implement high-speed interfaces in their systems. This workshop starts with an introduction to VERSAL ACAP including discussion on the IO and clocking resources. Signal interfacing is discussed in detail before discussing in depth designing for DDR4 and serial transceivers. Special focus is on the Network-on-Chip (NoC) as new high-performance connectivity structure inside ACAP devices.

All design steps are described: IP configuration, functional simulation, and implementation. Designs will be verified on real hardware once VERSAL boards are available. Additional focus is put on the physical layer – PCB design and signal integrity. Practical design and verification examples are discussed. Students learn how to apply design rules to the PCB design. Methodical tips and tricks are provided throughout the training. Exercises in VERSAL ACAP devices intensify students’ acquired knowledge.


Applicable technologies

  • Versal ACAP

Requirements

  • Basic knowledge on VHDL implementation

Dates


02.11.2020 | Stuttgart
Booking

Duration & Fee


Duration: 3 days

Fee: 2,100.00 €
net per person including detailed training material

Contact


Michael Schwarz

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