Understanding Versal: The Architecture - WEBINAR

This session will have a look at the architecture of Versal® ACAP understanding its architecture and how it can be used. First, we describe the Versal ACAP architecture at a high level, identify the various engines in the Versal ACAP device, and describe the NoC and memory hierarchy for on-chip and external memories. The ARM processing system and platform management controller provide the application development using embedded processors. DSP, AI, and adaptable engines will be used for acceleration tasks, and NoC the network for the hardware-accelerated system integration. Different types of I/O's will be explained like dedicated pins, SelectIO, related PHYs, Gigabit transceivers, and the coherent PCIe module which provides acceleration solutions for computer and server-based systems.

Registration:

Register for this webinar for free.

Date:

If the date does not suit you, you still have the possibility to watch this webinar. The webinar will be recorded and available "on demand" afterwards.

Live:

During the webinar you have time to ask questions directly to the trainer.

Language:

The course language is English.

Applicable technologies

• AMD Xilinx Versal Adaptive SoCs
• Versal Adaptive SoCs

Requirements

• none