Understanding Versal: The Adaptable Engines - WEBINAR

This is the third webinar of the PLC2 series: Understanding Versal.

This session will focus on the hardware adaptable architecture of Versal ACAP which provides the capability of hardware programmability to adapt all the Versal engines with additional digital functions and required interfaces. Based on UltraScale+ technology the Versal adaptable engines provide an improved and denser architecture as in previous technologies. The adaptable engines include the Configurable logic block (CLB), Block RAM memory array, and the UltraRAM memory array. The CLB and LUT architecture will be described in detail, the inclusion of latches and registers and using the memory resources of LUTRAM, BlockRAM, and UltraRAM, and which configurations can be used. And finally, the clock regions including the XPLLs, the on-chip topology and the clock routing structure, clock trees, clock buffers, and their management will be described.

Registration:

Register for this webinar for free.

Date:

If the date does not suit you, you still have the possibility to watch this webinar. The webinar will be recorded and available "on demand" afterwards.

Live:

During the webinar you have time to ask questions directly to the trainer.

Language:

The course language is English.

Applicable technologies

• XILINX Versal ACAP
• Versal ACAP

Requirements

• none