UltraScale/UltraScale+ Architecture - LIVE ONLINE

The UltraScale/UltraScale+ online training describes the hardware architecture of these devices. After a general introduction oft he ASML architecture the workshop focus on adetailled descriptions of the internal architectural blocks like RAMs (Distributed RAMs, BRAMs, ULTRA_RAMS) as well as Clock buffers, Slices and IOs.

The theoretical content is supplemented by exercises carried out by the participant.

Duration: 2 mornings of 4 hours each

Times:    9.00 a.m. - 11.00 a.m.    Lecture part 1

              11.00 a.m. - 11.15 a.m.  15 minute break

              11.15 a.m. - 1.15 p.m.     Lecture part 2

Exercises: self paced by the participants. Estimated time for completion appr. 2-3 hours. At the end of a lecture, the exercises to be performed by participants are discussed. The results / sample solutions are presented by the trainer the next day.

After registration: the participant receives the presentation documents in electronic form (PDF) as well as the workbook for the exercises, the login data and a list of 
requirements to be done in advanced.

Agenda:

• UltraScale Architecture Clocking Resources
• UltraScale Architecture Block RAM Memory Resources
• UltraScale Architecture FIFO Memory Resources
• UltraRAM Memory
• DDR4 Design Creation Using MIG
• UltraScale Architecture I/O Resources Overview

Applicable technologies

• UltraScale/UltraScale+ Technologies

Requirements

• Basic knowledge in VHDL
• Basic knowledge in digital design techniques
• Basic knowledge of XILINX Design Tool Flow