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UltraScale FPGAs – Connectivity

The Xilinx UltraScale architectures allow for very fast interfaces to external components based on significantly improved silicon structures as well as new IP Core configuration wizards.
Realization challenges are shifting from chip level to board level with the new UltraScale architectures. Extreme accuracy in PCB design is mandatory to achieve high-speed data rates.
The 5-day PowerWorkshop “UltraScale FPGAs - Connectivity” has been developed for hardware designers, system architects and layout designers who want to successfully implement high-speed interfaces in their systems. This workshop starts with an introduction to UltraScale FPGAs including discussion on the IO and clocking resources.
Signal interfacing is discussed in detail before discussing in depth designing for DDR4, serial transceivers and PCI Express interfaces. All design steps are described: IP configuration, functional simulation, and implementation. Designs are verified on real hardware. Additional focus is put on the physical layer – PCB design and signal integrity. Practical design and verification examples are discussed.
Simulation options on PCB level are described. Students learn how to apply design rules to the PCB design. Methodical tips and tricks are provided throughout the training.
Exercises in UltraScale FPGAs intensify students’ acquired knowledge.


Applicable technologies

  • UltraScale architectures

Requirements

  • Comfort with the VHDL programming language

Dates


08.03.2021 | Munich
Booking
26.07.2021 | Frankfurt
Booking
04.10.2021 | Berlin
Booking

Duration & Fee


Duration: 5 days

Fee: 3,100.00 €
net per person including detailed training material, beverages during breaks and lunch

Contact


Michael Schwarz

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